Patents by Inventor Sudharshanan Raghunthathan

Sudharshanan Raghunthathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SELF-ALIGNED VIA PROCESS FLOW
    Publication number: 20170004999
    Abstract: A device includes a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines are embedded in a second dielectric layer disposed above the first dielectric layer. A first conductive line in the first plurality of conductive lines contacts the conductive feature and includes a conductive via portion and a recessed line portion. A second plurality of conductive lines are embedded in a third dielectric layer disposed above the second dielectric layer. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the conductive via portion has a first cross-sectional dimension corresponding to a width of the first conductive line and a second cross-sectional dimension corresponding to a width of the second conductive line.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 5, 2017
    Inventors: Guillaume Bouche, Andy C. Wei, Sudharshanan Raghunthathan
  • Self-aligned via process flow
    Patent number: 9502293
    Abstract: A method includes forming a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines embedded in a second dielectric layer disposed above the first dielectric layer is formed. A first conductive line in the plurality of conductive lines contacts the conductive feature. The first conductive line is etched using a first etch mask to define a conductive via portion and a recessed line portion in the first conductive line. A second plurality of conductive lines embedded in a third dielectric layer disposed above the second dielectric layer is formed. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the third dielectric layer directly contacts the second dielectric layer.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: November 22, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Guillaume Bouche, Andy C. Wei, Sudharshanan Raghunthathan
  • SELF-ALIGNED VIA PROCESS FLOW
    Publication number: 20160141206
    Abstract: A method includes forming a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines embedded in a second dielectric layer disposed above the first dielectric layer is formed. A first conductive line in the plurality of conductive lines contacts the conductive feature. The first conductive line is etched using a first etch mask to define a conductive via portion and a recessed line portion in the first conductive line. A second plurality of conductive lines embedded in a third dielectric layer disposed above the second dielectric layer is formed. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the third dielectric layer directly contacts the second dielectric layer.
    Type: Application
    Filed: November 18, 2014
    Publication date: May 19, 2016
    Inventors: Guillaume Bouche, Andy C. Wei, Sudharshanan Raghunthathan