Abstract: A software simulation method and program storage device for software defect detection and obtaining insight into software code is disclosed, where simulation consists of executing target software program code for multiple input values and multiple code paths at the same time, thus achieving 100% coverage over inputs and paths without actually running the target software. This allows simulation to detect many defects that are missed by traditional testing tools. The simulation method runs a plurality of algorithms where a plurality of custom defined and pre-defined rules are verified in target software to find defects and obtain properties of the software code.

Abstract: A software simulation method and program storage device for software defect detection and obtaining insight into software code is disclosed, where simulation consists of executing target software program code for multiple input values and multiple code paths at the same time, thus achieving 100% coverage over inputs and paths without actually running the target software. This allows simulation to detect many defects that are missed by traditional testing tools. The simulation method runs a plurality of algorithms where a plurality of custom defined and pre-defined rules are verified in target software to find defects and obtain properties of the software code.

Abstract: A plurality of processor cores on a chip is operated in a normal fashion in a debug and diagnostic mode of operation of the processor. A crossbar switch on the chip couples and decouples the plurality of processors to a plurality of banks in a level-two (L2) cache that is also on the chip. As data is passed from each of the processor cores through the crossbar switch to the L2 cache, the data in cached in a first plurality of banks of the L2 cache. The commands associated with the data and information concerning the status of the data in the level-one cache are logged in another plurality of banks of the L2 cache. This logged information can be readout and used in diagnosis and debugging of L1 and L2 cache problems.

Abstract: A plurality of processor cores on a chip is operated in a normal fashion in a debug and diagnostic mode of operation of the processor. A crossbar switch on the chip couples and decouples the plurality of processors to a plurality of banks in a level-two (L2) cache that is also on the chip. As data is passed from each of the processor cores through the crossbar switch to the L2 cache, the data in cached in a first plurality of banks of the L2 cache. The commands associated with the data and information concerning the status of the data in the level-one cache are logged in another plurality of banks of the L2 cache. This logged information can be readout and used in diagnosis and debugging of L1 and L2 cache problems.

Abstract: A method and system for accurately validating performance and functionality of a processor in a timely manner is provided. First, a program is executed on a high level simulator of the processor. Next, a plurality of checkpoints are established. Then, state data at each of the checkpoints is saved. Finally, the program is run on a plurality of low level simulators of the processor in parallel, where each of the low level simulators is started at a corresponding checkpoint with corresponding state data associated with the corresponding checkpoint.

Abstract: A system and method for verifying a memory consistency model for a shared memory multiprocessor computer systems generates random instructions to run on the processors, saves the results of the running of the instructions, and analyzes the results to detect a memory subsystem error if the results fall outside of the space of possible outcomes consistent with the memory consistency model. A precedence relationship of the results is determined by uniquely identifying results of a store location with each result distinct to allow association of a read result value to the instruction that created the read result value. A precedence graph with static, direct and derived edges identifies errors when a cycle is detected that indicates results that are inconsistent with memory consistency model rules.

Abstract: A system and method for verifying a memory consistency model for a shared memory multiprocessor computer systems generates random instructions to run on the processors, saves the results of the running of the instructions, and analyzes the results to detect a memory subsystem error if the results fall outside of the space of possible outcomes consistent with the memory consistency model. A precedence relationship of the results is determined by uniquely identifying results of a store location with each result distinct to allow association of a read result value to the instruction that created the read result value. A precedence graph with static, direct and derived edges identifies errors when a cycle is detected that indicates results that are inconsistent with memory consistency model rules.