Patents by Inventor Sudheendra Srivathsa

Sudheendra Srivathsa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240185527
    Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
    Type: Application
    Filed: January 10, 2024
    Publication date: June 6, 2024
    Applicant: Intel Corporation
    Inventors: Subramaniam Maiyuran, Saurabh Sharma, Jorge F. Garcia Pabon, Raghavendra Kamath Miyar, Sudheendra Srivathsa, Justin Decell, Aditya Navale
  • Patent number: 11900539
    Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Subramaniam Maiyuran, Saurabh Sharma, Jorge F. Garcia Pabon, Raghavendra Kamath Miyar, Sudheendra Srivathsa, Justin Decell, Aditya Navale
  • Publication number: 20230095535
    Abstract: Dynamic tile sequencing in graphics processing is described. An example of an apparatus includes one or more processors including a graphics processor, the one or more processor including a plurality of portions and tile sequencing circuitry; and a memory to store data for graphics processing, including data for a render target and data for a hashing table, the render target including a plurality of tiles, and the hashing table to map the tiles of the render target to the plurality of portions of the one or more processors, wherein the tile sequencing circuitry includes a first mode for tile sequencing, wherein tile sequencing in the first mode includes a set granularity for the hashing table; and a second mode for tiling sequencing, wherein tile sequencing in the second mode includes a configurable granularity for the hashing table.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Applicant: Intel Corporation
    Inventors: Subramaniam Maiyuran, Jorge F. Garcia Pabon, Raghavendra Kamath Miyar, Sudheendra Srivathsa, Krishan Malik
  • Publication number: 20220262070
    Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
    Type: Application
    Filed: February 1, 2022
    Publication date: August 18, 2022
    Applicant: Intel Corporation
    Inventors: Subramaniam Maiyuran, Saurabh Sharma, Jorge F. Garcia Pabon, Raghavendra Kamath Miyar, Sudheendra Srivathsa, Justin Decell, Aditya Navale
  • Publication number: 20220198735
    Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises tiling hardware to perform tile based rendering of objects, including receiving a workload comprising a plurality of objects, performing batch formation to generate one or more batches of the plurality of objects, performing super tile fill sequencing for to determine one or more super tiles that are intersected by objects in each batch and compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects, wherein each super tile comprises a plurality of tiles.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Subramaniam Maiyuran, Jorge F. Garcia Pabon, Raghavendra Kamath Miyar, Sudheendra Srivathsa, Krishan Malik, Narsim Krishna, Rajalakshmi Athimoolam, Amit Mishra
  • Patent number: 11250627
    Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Subramaniam Maiyuran, Saurabh Sharma, Jorge F. Garcia Pabon, Raghavendra Kamath Miyar, Sudheendra Srivathsa, Justin Decell, Aditya Navale
  • Publication number: 20210407194
    Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
    Type: Application
    Filed: June 29, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Subramaniam Maiyuran, Saurabh Sharma, Jorge F. Garcia Pabon, Raghavendra Kamath Miyar, Sudheendra Srivathsa, Justin Decell, Aditya Navale