Abstract: Systems and methods for automatically enabling and disabling a purchase card based on predetermined preferences set by a cardholder are provided. The systems and methods enable users to set preferences in advance, and then automatically determine whether to accept or decline a transaction based on the preset preferences. The systems and methods may also implement a learning algorithm to develop preferences based on historical cardholder behavior.

Abstract: The technology disclosed relates to a STRADL file system that transparently deploys file blocks across multiple tiers of storage. In a cloud-based storage platform, multiple storage tiers host data via file system APIs. This includes a volatile storage (VS) tier with a VS API, a reliable non-volatile storage (RNVS) tier with a RNVS API, and a highly reliable non-volatile storage (HRNVS) tier with a HRNVS API. The STRADL file system provides an intermediary file system API that presents to a host system a single interface and translates get, put, and other file system requests into commands compatible with the VS API, the RNVS API, and the HRNVS API, without host system awareness of which of the multiple tiers holds requested data and metadata.

Abstract: The technology disclosed relates to a STRADL file system that transparently deploys file blocks across multiple tiers of storage. In a cloud-based storage platform, multiple storage tiers host data via file system APIs. This includes a volatile storage (VS) tier with a VS API, a reliable non-volatile storage (RNVS) tier with a RNVS API, and a highly reliable non-volatile storage (HRNVS) tier with a HRNVS API. The STRADL file system provides an intermediary file system API that presents to a host system a single interface and translates get, put, and other file system requests into commands compatible with the VS API, the RNVS API, and the HRNVS API, without host system awareness of which of the multiple tiers holds requested data and metadata.

Abstract: Systems and methods for automatically enabling and disabling a purchase card based on predetermined preferences set by a cardholder are provided. The systems and methods enable users to set preferences in advance, and then automatically determine whether to accept or decline a transaction based on the preset preferences. The systems and methods may also implement a learning algorithm to develop preferences based on historical cardholder behavior.

Abstract: Disclosed approaches for probing signals in a plurality of clock domains include inputting unsynchronized trigger signals from the plurality of clock domains to a plurality of instances of a multi-synchronizer circuit, respectively. Each instance of the multi-synchronizer circuit includes a plurality of synchronizer circuits. One or more of the plurality of synchronizer circuits synchronizes the respective unsynchronized trigger signal with one clock signal from the plurality of clock domains. Output of one of the one or more synchronizer circuits in each instance of the multi-synchronizer circuit is selected as a respective synchronized trigger signal. A trigger equation is evaluated based on a state of each respective synchronized trigger signal. A final trigger signal is generated based the evaluating of the trigger equation, a trigger marker is stored in a memory in response to a state of the final trigger signal, and states of probed signals are stored in the memory.

Abstract: The technology disclosed relates to a STRADL file system that transparently deploys file blocks across multiple tiers of storage. In a cloud-based storage platform, multiple storage tiers host data via file system APIs. This includes a volatile storage (VS) tier with a VS API, a reliable non-volatile storage (RNVS) tier with a RNVS API, and a highly reliable non-volatile storage (HRNVS) tier with a HRNVS API. The STRADL file system provides an intermediary file system API that presents to a host system a single interface and translates get, put, and other file system requests into commands compatible with the VS API, the RNVS API, and the HRNVS API, without host system awareness of which of the multiple tiers holds requested data and metadata.

Abstract: An embodiment of the present invention provides transmitter having a phase locked loop that has a dynamically controllable loop bandwidth. A transmit modulator is coupled to the PLL for performing vector modulation in response to transmission symbols. Each transmission symbol comprises an amplitude signal and a phase signal. A controller is coupled to the PLL and to the transmit modulator and is operable to detect when a criteria of the transmission symbols crosses a threshold and to adjust loop bandwidth in response to crossing the threshold. The criteria of the transmission symbols may be a function of the amplitude signal or a function of the phase signal, and may be the amplitude signal, a first derivative of the amplitude signal, a second derivative of the amplitude signal, a square of the amplitude signal, a derivative of the amplitude signal squared, the phase signal, or a derivative of the phase signal.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal with a plurality of phases. A switch is coupled to receive the RF clock, and is operative to select one of the plurality of phases. A phase detection circuit is coupled to the switch and is operable to receive a selected phase and to provide digital phase error samples indicative of a time difference between the reference clock and the selected phase.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. An interpolator is coupled to the phase detection circuit for performing a sample rate conversion between the reference clock and the clock derived from the RF clock signal.

Abstract: An embodiment of the present invention provides transmitter having a phase locked loop that has a dynamically controllable loop bandwidth. A transmit modulator is coupled to the PLL for performing vector modulation in response to transmission symbols. Each transmission symbol comprises an amplitude signal and a phase signal. A controller is coupled to the PLL and to the transmit modulator and is operable to detect when a criteria of the transmission symbols crosses a threshold and to adjust loop bandwidth in response to crossing the threshold. The criteria of the transmission symbols may be a function of the amplitude signal or a function of the phase signal, and may be the amplitude signal, a first derivative of the amplitude signal, a second derivative of the amplitude signal, a square of the amplitude signal, a derivative of the amplitude signal squared, the phase signal, or a derivative of the phase signal.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal with a plurality of phases. A switch is coupled to receive the RF clock, and is operative to select one of the plurality of phases. A phase detection circuit is coupled to the switch and is operable to receive a selected phase and to provide digital phase error samples indicative of a time difference between the reference clock and the selected phase.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. An interpolator is coupled to the phase detection circuit for performing a sample rate conversion between the reference clock and the clock derived from the RF clock signal.

Abstract: A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, e.g., 20 ps, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. The TDC circuit can also serve as a CMOS process strength estimator for analog circuits in large SoC dies. The circuit also employs power management circuitry to reduce power consumption to a very low level.

Abstract: A method for inserting code during execution of a process in a computing environment, including enabling taken branch traps on the process, intercepting a branch encountered during execution of the process, and redirecting processing of the branch instruction to a routine. The intercepting of the branch and the redirecting of processing may be performed by a trap handler.