Patents by Inventor Sudheer Kumar VEMULAPALLI

Sudheer Kumar VEMULAPALLI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Phase interpolator and a delay circuit for the phase interpolator
    Patent number: 8446198
    Abstract: Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The multiplexer is configurable using a first control signal to output one of the phase rotated signal and a phase shifted output of the plurality of phase shifted outputs. The delay cell delays one of the phase rotated signal and the phase shifted output to generate another phase shifted output of the plurality of phase shifted outputs.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: May 21, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Anant Shankar Kamath, Krishnaswamy Nagaraj, Sudheer Kumar Vemulapalli, Jayawardan Janardhanan, Karthik Subburaj, Sujoy Chakravarty, Vikas Sinha
  • PHASE INTERPOLATOR AND A DELAY CIRCUIT FOR THE PHASE INTERPOLATOR
    Publication number: 20110254603
    Abstract: Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The multiplexer is configurable using a first control signal to output one of the phase rotated signal and a phase shifted output of the plurality of phase shifted outputs. The delay cell delays one of the phase rotated signal and the phase shifted output to generate another phase shifted output of the plurality of phase shifted outputs.
    Type: Application
    Filed: April 16, 2010
    Publication date: October 20, 2011
    Applicant: Texas Instruments Incorporated
    Inventors: Anant Shankar KAMATH, Krishnaswamy NAGARAJ, Sudheer Kumar VEMULAPALLI, Jayawardan JANARDHANAN, Karthik SUBBURAJ, Sujoy CHAKRAVARTY, Vikas SINHA