Abstract: A computer-implemented processing tool is provided for facilitating debugging of simulation results obtained for an optimized simulation model of a device having hierarchically-connected components. The tool includes: receiving a component port name of the device to be searched; automatically checking a hardware descriptive language description of the device for a next higher level component of the device that instantiates the component having the component port name to be searched; locating a signal name in the next higher level component that is connected to the port identified by the component port name; and outputting the signal name as a signal that drives the named component port when the signal is other than a port signal of the next higher level component. Otherwise, repeating the automatically checking and the locating when the signal name in the next higher level component is a port signal of a further higher level component.

Abstract: A waveform viewer implemented method of generating and manipulating user specified language simulation code such that an integrated circuit digital design can be modified. The visual capabilities of the waveform viewer allow a plurality of inputs for processing. The previous test's user specified language lines and the original signal waveforms are viewable on the same screen as the new code lines and waveforms. The waveform viewer also displays the contents of the portable reusable code portable reusable coded storage device. Each line of code and every signal can be manipulated by the user within the waveform viewer. The modified code output is applied to the test sequence through the waveform viewer, and the integrated circuit is retested with the new code. After modifications to the integrated circuit are complete, the proved device's stored user specified language can be transported to and inserted in other device architectures.