Abstract: Aspects of the present invention provide a system and method for checking a portion of an analog circuit using a digital checker. The method includes establishing a target in the analog circuit, creating an analog target dummy for the target, creating a digital target dummy, binding the digital target dummy to the analog target dummy, and checking a value of the digital target dummy with a digital checker.

Abstract: Aspects of the present invention provide a system and method for checking a portion of an analog circuit using a digital checker. The method includes establishing a target in the analog circuit, creating an analog target dummy for the target, creating a digital target dummy, binding the digital target dummy to the analog target dummy, and checking a value of the digital target dummy with a digital checker.

Abstract: A device for receiving a RF signal over multiple channels, a receiver incorporating the device, a method of providing digital calibration values for a digitally-tunable resonant circuit of the device, and a method of processing an RF signal. In one embodiment the device includes: (1) a low-noise amplifier having a digitally-tunable resonant circuit, (2) a memory configured to store digital calibration values particular to the device and (3) a time-constant controller coupled to the low-noise amplifier and configured to retrieve from the memory at least one of the digital calibration values as a function of a channel to be received and, based on the at least one, to cause the digitally-tunable resonant circuit to provide a time-constant corresponding to the channel to be received.

Abstract: A device for receiving a RF signal over multiple channels, a receiver incorporating the device, a method of providing digital calibration values for a digitally-tunable resonant circuit of the device, and a method of processing an RF signal. In one embodiment the device includes: (1) a low-noise amplifier having a digitally-tunable resonant circuit, (2) a memory configured to store digital calibration values particular to the device and (3) a time-constant controller coupled to the low-noise amplifier and configured to retrieve from the memory at least one of the digital calibration values as a function of a channel to be received and, based on the at least one, to cause the digitally-tunable resonant circuit to provide a time-constant corresponding to the channel to be received.

Abstract: System and method for correcting an inaccurate clock with the use of an accurate reference clock. A preferred embodiment comprises repeatedly counting clock cycles in a clock signal generated by the inaccurate clock for a specified period of time, after the completion of each specified period of time, computing a delta value based on the clock cycle counts of the clock signal of the inaccurate clock, accumulating a delta sum value, and computing a clock adjustment value for the inaccurate clock based upon the delta sum value. The reference clock is used to mark the end of each specified period of time.

Abstract: System and method for correcting an inaccurate clock with the use of an accurate reference clock. A preferred embodiment comprises repeatedly counting clock cycles in a clock signal generated by the inaccurate clock for a specified period of time, after the completion of each specified period of time, computing a delta value based on the clock cycle counts of the clock signal of the inaccurate clock, accumulating a delta sum value, and computing a clock adjustment value for the inaccurate clock based upon the delta sum value. The reference clock is used to mark the end of each specified period of time.

Abstract: A turbo encoder includes a memory for temporarily storing an incoming data sequence and an interleaved address generator (IAG) designed to generate a sequence of addresses corresponding to the interleaved data sequence. The IAG performs calculations based on the length of the incoming data sequence and is able to generate a first interleaved address by (or before) the time the incoming data sequence has completely shifted into the memory. As a result, the encoder begins to output encoded data substantially as soon as the corresponding incoming data have been received, thus substantially reducing the processing delay. In addition, each interleaved address can be generated on the fly as needed during data output. As a result, the entire set of interleaved addresses does not need to be stored, thus reducing the memory requirements for the encoder.

Abstract: For generating coefficients of an expanded polynomial, n-roots, each respective coefficient is generated at a respective one of (n+1) coefficient storage registers at one of a first place at a right most place to a (n+1) place at a left most place. In addition, a temporary coefficient is stored as the respective coefficient that was at the first place in a prior clock cycle. Such coefficients are initialized, and then an ith order multiplier output is generated by multiplying an ith order root with the respective coefficient at the first place, and an ith order adder output is generated by adding the temporary coefficient to the ith order multiplier output. The respective coefficients at and to the right of an (i+1) place are shifted toward the right with the respective coefficient at the first place becoming the temporary coefficient. The ith order adder output then becomes the respective coefficient at the (i+1) place.