Patents by Inventor Sudhir Dhawan
Sudhir Dhawan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9251346Abstract: Preventing propagation of hardware viruses in a computing system, including: determining, by a hardware virus detection module, whether an empty connector in the computing system is damaged, wherein the empty connector is blocked from receiving an attachable computing device by a bumper; determining, by the hardware virus detection module, whether a connector for the attachable computing device is damaged; and responsive to determining that the empty connector is not damaged and that the connector for the attachable computing device is not damaged, moving the bumper such that the empty connector is not blocked from receiving the attachable computing device.Type: GrantFiled: February 27, 2013Date of Patent: February 2, 2016Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Shiva R. Dasari, Sudhir Dhawan, Raghuswamyreddy Gundam, Joshua H. Israel, Karthik Kolavasi, Newton P. Liu, Douglas W. Oliver, Mehul M. Shah, Wingcheung Tam
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Publication number: 20140245445Abstract: Preventing propagation of hardware viruses in a computing system, including: determining, by a hardware virus detection module, whether an empty connector in the computing system is damaged, wherein the empty connector is blocked from receiving an attachable computing device by a bumper; determining, by the hardware virus detection module, whether a connector for the attachable computing device is damaged; and responsive to determining that the empty connector is not damaged and that the connector for the attachable computing device is not damaged, moving the bumper such that the empty connector is not blocked from receiving the attachable computing device.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shiva R. Dasari, Sudhir Dhawan, Raghuswamyreddy Gundam, Joshua H. Israel, Karthik Kolavasi, Newton P. Liu, Douglas W. Oliver, Mehul M. Shah, Wingcheung Tam
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Patent number: 8140937Abstract: A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.Type: GrantFiled: January 4, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Shiva R. Dasari, Sudhir Dhawan, Joseph Allen Kirscht, Jennifer L. Vargus
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Publication number: 20090177946Abstract: A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.Type: ApplicationFiled: January 4, 2008Publication date: July 9, 2009Inventors: Shiva R. Dasari, Sudhir Dhawan, Joseph Allen Kirscht, Jennifer L. Vargus
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Patent number: 7447934Abstract: A method, system, and program product for recovering from a bus error in a computer system having a hot plug interface. In accordance with the method of the present invention, an operating system transparent interrupt, such as a system management interrupt, is generated in response to a bus error. Responsive to the operating system transparent interrupt, the hot pluggable bus is scanned and a device associated with the error is identified by an interrupt handler invoked by the interrupt. Finally, a hot plug configuration manager, such as an advanced configuration and power interface is utilized to remove the identified device from system operations without having to restart the system.Type: GrantFiled: June 27, 2005Date of Patent: November 4, 2008Assignee: International Business Machines CorporationInventors: Shiva R. Dasari, Sudhir Dhawan, Ryuji Orita, Wingcheung T. Tam
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Patent number: 7251185Abstract: In an aspect, a method is provided for using memory. The method includes the steps of (1) employing memory stacking, memory mirroring and memory interleaving in a total memory to reduce a number of memory entries that are written to an input/output (I/O) device while a portion of the total memory is replaced; and (2) storing data in the total memory. Numerous other aspects are provided.Type: GrantFiled: February 24, 2005Date of Patent: July 31, 2007Assignee: International Business Machines CorporationInventors: John M. Borkenhagen, Sudhir Dhawan, Philip R. Hillier, III, Joseph A. Kirscht, Randolph S. Kolvick
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Publication number: 20070124543Abstract: An apparatus, system, and method are disclosed for externally invalidating an uncertain cache line. In one embodiment, a monitor module monitors a processor module bus. A detection module detects a processor module evicting a cache line from a cache module. The cache line may be in an uncertain state. An invalidation module invalidates the cache line with an invalidation command directed to the processor module. In one embodiment, an update module updates a cache directory external to the processor module. The apparatus, system, and method increase memory and processor bandwidth by eliminating the need to snoop the processor module bus for evicted cache lines.Type: ApplicationFiled: November 28, 2005Publication date: May 31, 2007Inventors: Sudhir Dhawan, James Nicholson
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Publication number: 20070011500Abstract: A method, system, and program product for recovering from a bus error in a computer system having a hot plug interface. In accordance with the method of the present invention, an operating system transparent interrupt, such as a system management interrupt, is generated in response to a bus error. Responsive to the operating system transparent interrupt, the hot pluggable bus is scanned and a device associated with the error is identified by an interrupt handler invoked by the interrupt. Finally, a hot plug configuration manager, such as an advanced configuration and power interface is utilized to remove the identified device from system operations without having to restart the system.Type: ApplicationFiled: June 27, 2005Publication date: January 11, 2007Applicant: International Business Machines CorporationInventors: Shiva Dasari, Sudhir Dhawan, Ryuji Orita, Wingcheung Tam
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Publication number: 20060187739Abstract: In an aspect, a method is provided for using memory. The method includes the steps of (1) employing memory stacking, memory mirroring and memory interleaving in a total memory to reduce a number of memory entries that are written to an input/output (I/O) device while a portion of the total memory is replaced; and (2) storing data in the total memory. Numerous other aspects are provided.Type: ApplicationFiled: February 24, 2005Publication date: August 24, 2006Applicant: International Business Machines CorporationInventors: John Borkenhagen, Sudhir Dhawan, Philip Hillier, Joseph Kirscht, Randolph Kolvick
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Patent number: 6378027Abstract: A method of servicing a processor array of a computer system by quiescing a processor selected for maintenance and removing the selected processor from a processor pool used by the computer's operating system. The selected processor is then powered down while maintaining power to and operation of other processors in the processor array. The selected processor may be identified as being defective, or may have been selected for upgrading. The processor array may include several processor clusters, such that the quiescing, removing and powering down steps apply to all processors in one of the processing clusters. The operating system assigns one of the processors in the processor array to be a service processor, and if the service processor is the processor selected for maintenance, the OS re-assigns the service processor functions to another processor in the processor array.Type: GrantFiled: March 30, 1999Date of Patent: April 23, 2002Assignee: International Business Machines CorporationInventors: Richard Bealkowski, Sudhir Dhawan, Kenneth Claude Hinz, Peter Matthew Thomsen
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Patent number: 6295591Abstract: A method of providing maintenance for a memory device of a computer system without interrupting operation of the computer system, by partially mirroring a primary memory array in a secondary memory array, wherein the secondary memory array has a different amount of available memory than the primary memory array. Values are copied from the primary memory array to the permanent storage device, allowing the primary memory array to quiesce and be serviced while using the secondary memory array to operate the computer system. Thereafter, the primary memory array is brought on-line, and the mirrored values are written back from the secondary memory array to the primary memory array. The memory service program itself may be embedded in the operating system. In an illustrative embodiment, the primary memory array is located on a first removable memory card, and the secondary memory array is located on a second removable memory card. The amount of memory available in the secondary memory array may be programmable.Type: GrantFiled: March 30, 1999Date of Patent: September 25, 2001Assignee: International Business Machines CorporationInventors: Richard Bealkowski, Scott Douglas Clark, Sudhir Dhawan, Robert Allen Drehmel
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Patent number: 6262890Abstract: A device for solving the electrical, physical, architectural and thermal challenges associated with designing a computer system is disclosed. A memory controller chipset having two or more chips mounted on opposite sides of a system planar helps balance the thermal profile of the system and achieve the strict spacing requirements of advanced computer processors relative to the memory controller chipset. Although the chips are staggered on opposite sides of the system planar, the adjacent edges of the chips substantially align with one another to minimize their separation.Type: GrantFiled: March 18, 1999Date of Patent: July 17, 2001Assignee: International Business Machines CorporationInventors: Sudhir Dhawan, Mark Wayne Mueller, Peter Matthew Thomsen, Lucinda Mae Walter
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Patent number: 5491811Abstract: Apparatus and method for improving the rate of transfer of data in the context of a system memory operated in conjunction with a cache. In one form, mask bits in a mask bit register are associated to bytes of cache. The mask bits are changed in state when the corresponding byte in the cache is written. The mask bits are used in a reordered operating sequence to selectively write data from system memory into the cache after a write into cache. Data transfer performance is improved significantly in that the selective writing of data from system memory to cache can be completely eliminated when the mask bits indicate that a whole unit of the cache, typically a cache line, has been written during the data transfer into the cache.Type: GrantFiled: April 20, 1992Date of Patent: February 13, 1996Assignee: International Business Machines CorporationInventors: Ravi K. Arimilli, Sudhir Dhawan, David W. Siegel
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Patent number: 5287482Abstract: A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Virtual memory addresses used by the input/output devices are translated into real addresses in the system memory. Virtual memory can be partitioned, with some virtual addresses being mapped to a second memory attached to the input/output bus.Type: GrantFiled: July 9, 1992Date of Patent: February 15, 1994Assignee: International Business Machines CorporationInventors: Ravi K. Arimilli, Sudhir Dhawan, James O. Nicholson, David W. Siegel
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Patent number: 5287457Abstract: A DMA controller coupled to two separate buses controls the transfer of data between them. To effect a block data transfer, data is simultaneously read on one bus and written on the other. This allows data to be transferred between buses at the maximum transfer rate supported by the slower bus.Type: GrantFiled: April 15, 1992Date of Patent: February 15, 1994Assignee: International Business Machines CorporationInventors: Ravi K. Arimilli, Sudhir Dhawan, James O. Nicholson, David W. Siegel
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Patent number: 5274784Abstract: A computer system can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.Type: GrantFiled: November 13, 1991Date of Patent: December 28, 1993Assignee: International Business Machines CorporationInventors: Ravi K. Arimilli, Sudhir Dhawan, James O. Nicholson, David W. Siegel
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Patent number: 5237676Abstract: A computer system bus includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.Type: GrantFiled: January 13, 1989Date of Patent: August 17, 1993Assignee: International Business Machines Corp.Inventors: Ravi K. Arimilli, Sudhir Dhawan, George A. Lerom, James O. Nicholson, David W. Siegel
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Patent number: 5109490Abstract: A computer system can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.Type: GrantFiled: January 13, 1989Date of Patent: April 28, 1992Assignee: International Business Machines CorporationInventors: Ravi K. Arimilli, Sudhir Dhawan, James O. Nicholson, David W. Siegel