Abstract: This application discloses a computing system implementing tools and mechanisms that can incorporate a security co-processor into a circuit design modeling an electronic device. The tools and mechanisms can configure the security co-processor to monitor at least a portion of the electronic device. The tools and mechanisms can generate at least one security action for the security co-processor to initiate when the security co-processor monitors the electronic device failing to conform to rules in a rules database.

Abstract: The application discloses a computing system to analyze a program to generate a control flow graph representing paths capable of being traversed through the program during execution. The computing system can translate the control flow graph into a constraint graph representation of the program. The computing system can utilize a constraint solver on the constraint graph to identify a set of test values associated with a coverage definition. The set of test values can prompt the program, during execution, to be exercised based on the coverage definition provided to the test program generation tool 300. The computing system can generate a test program configured to provide the set of input variable values to the program.

Abstract: This application discloses a computing system implementing tools and mechanisms that can incorporate a security co-processor into a circuit design modeling an electronic device. The tools and mechanisms can configure the security co-processor to monitor at least a portion of the electronic device. The tools and mechanisms can generate at least one security action for the security co-processor to initiate when the security co-processor monitors the electronic device failing to conform to rules in a rules database.

Abstract: A method of implementing a traversal strategy as part of a dynamic verification can include initializing a non-deterministic automaton (NDA) traversal mechanism that has (1) a strategy push-down stack (strategy PDS) that holds traversal strategy pointers and (2) an object push-down stack (object PDS) that holds object pointers, pushing a traversal strategy object pointer onto the strategy PDS, wherein the traversal strategy object pointer points to a traversal strategy object, popping a current object pointer from the object PDS, and determining whether the current object pointer points to a terminal object.

Abstract: A method and apparatus for synchronizing a non-deterministic automaton being processed on a computing device during dynamic verification of a system or device under test, is described herein.

Abstract: A method and apparatus for resource management for non-deterministic automata for dynamic verification of a system or device under test is described herein.