Abstract: A method for tokenizing assets via a blockchain-to-blockchain bridge may include: receiving a first instruction from a client to mint first tokens for a client asset; encumbering the client asset on a custody ledger; creating a balance of the first tokens on a first distributed ledger; receiving a second instruction to lock and mint the first tokens to a second distributed ledger as second tokens; receiving verification from a custodian that the first tokens are locked on a lock ledger for the custodian; instructing a blockchain bridge computer program to mint second tokens to a client address on the second distributed ledger; receiving a third instruction to return the second tokens to the first distributed ledger; executing a public burn of the second tokens on the second distributed ledger; and instructing the custodian to unlock the first tokens and move the first tokens to the first distributed ledger.

Abstract: Composite hollow fiber gas separation membranes with improved permeance and separation layer adhesion are manufactured by providing dipping a hollow fiber membrane substrate in a pre-coat layer coating composition followed by drying to thereby provide a pre-coated substrate and dipping the pre-coated substrate in a separation layer coating composition followed by drying to thereby provide the composite hollow fiber gas separation membranes. The pre-coating composition includes a first polymer dissolved in a first solvent and the separation layer composition includes a second polymer dissolved in a second solvent. The first and second polymers are the same or different, each of the first and second polymers is at least 1 wt % soluble in a same third solvent, the first and second solvents are the same or different, the first and third solvents are the same or different, and the second and third solvent are the same or different.

Abstract: Described herein are absorbent compositions and methods of making and using the compositions. The absorbent composition including a hydrophilic cellulosic material functionalized with one or more hydrophobic chemical modification agents. The one or more hydrophobic chemical modification agents can be polymerized with or grafted to the hydrophilic cellulosic material via a chemical, physical or ionic bonds. The hydrophilic cellulosic material can exhibit an increased level of hornification. The method of making the absorbent composition including: a) contacting a hydrophilic cellulosic material with one or more hydrophobic chemical modification agents to form a precursor mixture; and b) allowing the one or more hydrophobic chemical modification agents to react with the hydrophilic cellulosic material to form an absorbent composition. The absorbent composition may be used for selective oil absorption and/or chloroform absorption.

Abstract: A computer-implemented method comprising, receiving, by one or more processors, a request to create a listing for a purchase of a product or service, wherein a quantity of greater than two of the product or service is required, analyzing, by one or more processors, a set of requirements to purchase the product or service based on a set of seller's requirements, applying, by one or more processors, the set of seller requirements to the listing, wherein the listing is depicted within a user interface, determining, by one or more processors, if a length of time restrictions has expired or a predetermined number of purchasers have joined the listing to purchase the product or service, wherein a user interface is manipulated based on the determination, and processing, by one or more processors, the listing based on the determination.

Abstract: The present invention relates to novel isoxazole compounds of formula (I) having (PPAR) agonist activity, pharmaceutical compositions containing such compounds and methods for their use.

Abstract: The present invention relates to novel hypolipidemic, antiobesity, hypocholesterolemic and antidiabetic compounds. More particularly, the present invention relates to novel alkyl carboxylic acids of the general formula (I), their stereoisomers, pharmaceutically acceptable salts thereof and pharmaceutical compositions containing them where all symbols are as defined in the description.

Abstract: Processing circuiter 100 is provided having a passive data transfer capability. Processing circuitry 100 includes a bus 116, a first subsystem 105 coupled to bus 116 through first passive transfer logic 120a, and a second subsystem 108 coupled to bus 116 through second passive transfer logic 120b. Processing circuitry 100 further includes control circuitry 101/103 coupled to bus 116 for initiating a passive data transfer between first and second subsystems 105 and 108, first and second passive transfer logic 120a and 120b there after controlling exchange of data between the first and second subsystems 105 and 108 independent of the control circuitry 101/103.

Abstract: Display control circuitry is provided which includes a frame buffer 104 having a plurality of memory spaces 301 each for storing a block of display data. Circuitry 200 is provided for generating display position data representing a position on a display screen corresponding to a current display pixel being generated. For each memory space 301, a window control circuit 201 is provided for controlling the transfer of a block of data from the given memory space 301 to a selected window on the display screen. Each window control circuit 201 includes first registers 205, 206 for storing data defining horizontal boundaries of the window, second registers 210, 211 for storing data defining vertical boundaries of the window, and circuitry 207, 208, 209, 212, 213, 214 for comparing the display position data with data stored in the first and second registers and generate an enable signal when the position on the screen of the current pixel is within the window boundaries.

Abstract: A display controller 104 for use with a display device 107 operable to display images on a screen. Display controller 104 includes circuitry 201-210 for presenting first data to the display device 107 for generating an image in a first areas of the screen, the first data being retrieved from an external frame buffer 108. A display controller 104 further includes circuitry 205, 210 for presenting second data to the display device 107 for generating an image in the second area of the screen, the second data being retrieved from an internal frame buffer 206.

Abstract: A memory system 104 includes an array 200 of memory cells arranged in rows and columns. Circuitry 208 is included for selectively performing logic operations on a bit of data stored in a selected cell using a bit of received modifying data and mode data bit for selecting a logic operation for performance. Circuitry 208 for performing logic operations is operable during an AND logic operation to write data into the cell when the bit of modifying data is a logic zero and maintaining an existing bit stored in the cell when the bit of modifying data is a logic one. Also included is circuitry 207, 210 for receiving and latching the mode data bit and the modifying data through a single port.

Abstract: A memory system 104 includes an array 200 of memory calls arranged in rows and columns and circuitry 208 for selectively performing logic operations on a bit of data stored in a selected call using a bit of received modifying data and a mode data bit for selecting a logic operation for performance. Circuitry 208 for modifying during an OR logic operation writing bit of the modifying data into the cell when the bit of modifying data is a logic one and maintaining an existing bit stored in call when the bit of modifying data is a logic zero. Memory system 104 further includes circuitry 207, 210 for receiving and latching the mode data and the modifying data through a single port.

Abstract: Sensing circuitry including a sense amplifier 400 for latching a bit of data on a true bit line and a complementary bit of data on a complementary bit line. Circuitry 403, 404, 405 is included for performing boolean operations on bit of data latched in sense amplifier 400 in response to a bit of modifying data. Circuitry 403, 404, 405 during an AND operation pulls down the true bit line when the bit of modifying data a logic 0.

Abstract: A memory 600 including an array of memory cells 201 and a plurality of input/output terminals 220 for receiving control bits during control cycles and accessing selected ones of the cells 201 during data access cycles. A command bit input terminal 221 is provided for receiving command bits for initiating the control cycles and a mapping input terminal 222 is provided for receiving a mapping enable signal to initiate a mapping mode. Circuitry 215/ 216 is provided for decoding control bits received during at least one control cycle occurring during a mapping mode for allowing a mapping of a set of addresses for accessing the cells of the array 201.

Abstract: A memory including a plurality of input/output terminals 220 for exchanging data bits during a data access cycle and receiving command and control bits during a command and control cycle. The memory further includes an array of memory cells 201, a data input/output circuitry for transferring data between the input/output terminals and the array of memory cells during the data access cycle, and control circuitry for controlling operations of the memory in response to command and control bits received at the input/output terminals during the command and control cycle.

Abstract: A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

Abstract: A memory system 104 is provided which includes an array 200 of memory cells arranged in rows and columns. Circuitry 207, 208, 209, 210 is also provided for selectively performing logic operations on a bit of data stored in a selected memory cell using a bit of received modifying data. Circuitry 207, 208, 209, 210 for performing logic operations is operable during an AND operation to write the bit of modifying data into the selected memory cell when the bit of modifying data is a logic zero and maintains an existing bit stored in the selected cell when the bit of modifying data is a logic one.

Abstract: A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

Abstract: A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

Abstract: Methods are provided for transferring a stream of video data from a video data source to a display interface unit 20. A video data word is clocked into a first-in-first-out memory 30 by a first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

Abstract: A memory device 200 which includes a multiplexed address/data input/output 230. Circuitry 200 is based around an array 201 of memory cells and includes circuitry 202, 204 for addressing at least one of the cells in the array in response to at least one address bit and circuitry 208, 210, 211, 212 for exchanging data with an addressed one of the cells. Memory device 200 also includes control circuitry 206 operable to pass an address bit presented at the multiplexed input/output to the circuitry for addressing during a first time period and allow for the exchange of data between the circuitry for exchanging and multiplexed input/output during a second time period.