Abstract: A method includes contacting a first group of through-silicon vias (TSVs) contacts with a multi-contact probe and applying a first voltage value to each of the first group of TSV contacts via the multi-contact probe, where the first group of TSV contacts corresponds to a first group of TSVs. The method also includes determining, based on a second voltage value detected at a particular TSV of the first group of TSVs, whether the particular TSV corresponds to a TSV test result.

Abstract: A method includes contacting a first group of through-silicon vias (TSVs) contacts with a multi-contact probe and applying a first voltage value to each of the first group of TSV contacts via the multi-contact probe, where the first group of TSV contacts corresponds to a first group of TSVs. The method also includes determining, based on a second voltage value detected at a particular TSV of the first group of TSVs, whether the particular TSV corresponds to a TSV test result.

Abstract: Stacked IC devices (or 3D semiconductor devices) have two or more semiconductor devices stacked so they occupy less space than two or more conventionally arranged semiconductor devices. Access to test infrastructures of stacked ICs is provided, regardless of configuration, while using a reduced number of interface pins. A master test controller is provided in a base die and at least one slave test controller is provided in another die. The master test controller is coupled to a test data control (TDC) bus and is configured to broadcast test instructions, test data, and an ID of a slave test controller. The slave test controller is also coupled to the TDC bus, is configured to recognize the broadcast test instructions and test data addressed to the slave test controller, and responds to the instructions when the instructions are addressed to the slave test controller.

Abstract: Stacked integrated circuits (ICs) having a base component and secondary component are tested. The base component has a scan input pad, a scan output pad, a base scan chain, and a base chain access block including a base chain select multiplexor and a base bypass multiplexor. The secondary component has a secondary scan chain and a secondary chain access block including a secondary chain select multiplexor and a secondary bypass multiplexor. The secondary chain select multiplexor is configured to receive input directly from the base component and another component. The base and secondary chain access blocks are configured to selectively access the base scan chain and/or the secondary scan chain.

Abstract: A general test application scheme is proposed for existing scan-based BIST architectures. The objective is to further improve the test quality without inserting additional logic to the Circuit Under Test (CUT). The proposed test scheme divides the entire test process into multiple test sessions. A different number of capture cycles is applied after scanning in a test pattern in each test session to maximize the fault detection for a distinct subset of faults. A procedure is presented to find the optimal number of capture cycles following each scan sequence for every fault. Based on this information, the number of test sessions and the number of capture cycles after each scan sequence are determined to maximize the random testability of the CUT.

Abstract: An almost full-scan method and system for detecting faults in circuits can achieve higher fault coverages and significantly shorter test application time as compared with full-scan techniques. A special flip-flop selection of strategy is further described which permits implementation of the almost full-scan BIST method and system.

Abstract: A method for testing a controller-data path RTL circuit using a BIST scheme without imposing any major design restrictions on the circuit. A state table is extracted from the controller netlist of the circuit using a state machine extraction program. The untested RTL elements/modules in the circuit are then selected, and the test control and data flow (TCDF) of the circuit are extracted from the controller/data path. Once the TCDF is extracted for the selected RTL elements, a symbolic testability analysis (STA) is performed to obtain test environments for as many untested data path elements as possible. The controller input sequence at the select signals of these test multiplexers needed for the particular test environment is noted and/or stored. A BIST controller is synthesized from the stored input sequences and the circuit is integrated with the BIST components using the thereby determined BIST architecture.

Abstract: A technique is provided for testing an IC which includes a plurality of flip-flops. The flip-flops are arranged in at least one scan chain. The testing technique of the invention is practiced by selectively partitioning the scan chain into smaller scan chains so that the smaller chains can be simultaneously latched and provide test results. The scan chain is switchable between a partitioned and a non-partitioned configuration, so that either configuration can be selected on demand, thereby allowing both BIST and deterministic testing to be performed efficiently on the same circuit.

Abstract: A test point selection method for scan-based built-in self-test (BIST). The method calculates a hybrid cost reduction (HCR) value as an estimated value of the corresponding actual cost reduction for all nodes in a circuit under test. A test point is then selected having a largest HCR. This iterative process continues until the fault coverage of the circuit under test reaches a desired value or the number of test points selected is equal to a maximum number of test points. In an alternative embodiment, the cost reduction factor is calculated for all nodes in the circuit under test, the HCR is calculated for only a selected set of candidates, and the candidate having the largest HCR is selected as the test point. The test point selection method achieves higher fault coverage results and reduces computational processing relative to conventional selection methods.

Abstract: A scan-based BIST architecture for detecting path-delay faults in a sequential circuit converted to a combinational circuit or a less complex sequential circuit including a combinational portion and a plurality of scan flip-flops. The BIST structure includes a test pattern generator for generating two test patterns and a controller for generating a clock signal and an extended scan mode signal which is held high for two clock cycles while the output response of the combinational portion to the first and second test vectors is latched into the scan flip-flops in order to detect a signal transition. The invention is further directed to a method for detection of path-delay faults using this scan-based BIST architecture. To improve the fault coverage for path-delay faults, observation points may be inserted at the inputs of selected scan flip-flops. A predetermined number of scan flip-flops having the highest activation frequency are selected as the observation points.

Abstract: Built-In Self-Testing of multiple scan chains (12.sub.1 -12.sub.n)can be accomplished by providing separate clock signals (CK.sub.1 -CK.sub.n) that are scheduled by a control circuit (22) so that each chain is clocked at its rated frequency.