Abstract: Training data is collected for each training integrated circuit (IC) design of a set of training IC designs by: extracting a first set of IC design features in a first stage of an IC design flow, and extracting a first set of IC design labels in a second stage of the IC design flow, where the first stage of the IC design flow occurs earlier than the second stage of the IC design flow in the IC design flow. Next, a machine learning model is trained based on the training data.

Abstract: Training data is collected for each training integrated circuit (IC) design of a set of training IC designs by: extracting a first set of IC design features in a first stage of an IC design flow, and extracting a first set of IC design labels in a second stage of the IC design flow, where the first stage of the IC design flow occurs earlier than the second stage of the IC design flow in the IC design flow. Next, a machine learning model is trained based on the training data.

Abstract: Systems and techniques for optimizing a circuit design are described. Some embodiments reduce the number of gates in the library (e.g., by dynamically pruning the library) which are considered for optimization. Some embodiments create a linear delay model, and use the linear delay model instead of a non-linear delay model to substantially reduce the amount of computation required to check whether or not a particular replacement gate improves one or more metrics of the circuit design. Some embodiments determine an order for processing the gates in the library or for processing input pins of a gate to facilitate early rejection of a candidate gate in the library of gates. In some embodiments, the evaluation of the impact of a candidate gate transformation is done progressively and level-by-level only up to the point where the gate transformation degrades one or more metrics.

Abstract: Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order.

Abstract: Systems and techniques for optimizing a circuit design are described. Some embodiments reduce the number of gates in the library (e.g., by dynamically pruning the library) which are considered for optimization. Some embodiments create a linear delay model, and use the linear delay model instead of a non-linear delay model to substantially reduce the amount of computation required to check whether or not a particular replacement gate improves one or more metrics of the circuit design. Some embodiments determine an order for processing the gates in the library or for processing input pins of a gate to facilitate early rejection of a candidate gate in the library of gates. In some embodiments, the evaluation of the impact of a candidate gate transformation is done progressively and level-by-level only up to the point where the gate transformation degrades one or more metrics.

Abstract: A leakage power optimization system optimizes leakage power of a circuit design which includes a set of logic gates. The system selects a leakage-power-reducing transformation for a logic gate, and determines a zone around the logic gate. This zone includes logic gates within a first predetermined number of levels in the logic gate's fan-out, the logic gate's fan-in, and a second predetermined number of levels in the logic gate's fan-in's fan-out. The system propagates arrival times within the zone to obtain updated slack values at endpoints of the zone. Then, in response to determining that the updated slack values at the endpoints of the zone do not degrade one or more circuit timing metrics, the system applies the leakage-power-reducing transformation to the logic gate.

Abstract: A leakage power optimization system optimizes leakage power of a circuit design which includes a set of logic gates. The system selects a leakage-power-reducing transformation for a logic gate, and determines a zone around the logic gate. This zone includes logic gates within a first predetermined number of levels in the logic gate's fan-out, the logic gate's fan-in, and a second predetermined number of levels in the logic gate's fan-in's fan-out. The system propagates arrival times within the zone to obtain updated slack values at endpoints of the zone. Then, in response to determining that the updated slack values at the endpoints of the zone do not degrade one or more circuit timing metrics, the system applies the leakage-power-reducing transformation to the logic gate.

Abstract: Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order.