Patents by Inventor Sudipto NASKAR
Sudipto NASKAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12369399Abstract: An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.Type: GrantFiled: August 25, 2021Date of Patent: July 22, 2025Assignee: INTEL CORPORATIONInventors: Willy Rachmady, Sudipto Naskar, Cheng-Ying Huang, Gilbert Dewey, Marko Radosavljevic, Nicole K. Thomas, Patrick Morrow, Urusa Alaan
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Publication number: 20250218868Abstract: An integrated circuit device includes (i) a first interconnect feature extending within a first dielectric material, and (ii) a second interconnect feature extending within the first dielectric material, and landing on the first interconnect feature. The integrated circuit device further includes a layer having a first section and a second section, wherein the layer includes a second dielectric material that is compositionally different from the first dielectric material. An opening between the first section and the second section is above, and vertically aligned to, the first interconnect feature. The second interconnect feature extends through the opening. In an example, each of the first section and the second section is vertically separated from the first interconnect feature by at least 2 nanometers (nm). In an example, a dielectric constant of the second dielectric material is higher than a dielectric constant of the first dielectric material by at least 5%.Type: ApplicationFiled: December 27, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Sudipto Naskar, Christopher J. Jezewski, Akshit Peer, Ananya Dutta, Jiun-Ruey Chen, Matthew V. Metz, Mauro J. Kobrinsky, Bryce C. Walker, Dominic Esan, Weimin C. Han
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Publication number: 20250212464Abstract: Described herein are nanoribbon transistors with bilayer cavity spacers deposited near the ends of the nanoribbons, including between the ends of adjacent nanoribbons. The cavity spacers include a first, inner layer next to the gate stack, and a second, outer layer next to the source or drain. The inner layer may be a low-k dielectric material, while the outer layer may be a high-k dielectric material.Type: ApplicationFiled: December 22, 2023Publication date: June 26, 2025Applicant: Intel CorporationInventors: Sudipto Naskar, Shao Ming Koh, Chun Kuo Huang, Corey Joiner
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Publication number: 20250210411Abstract: In a metallization layer of an integrated circuit device, air gaps are formed between adjacent metal lines, e.g., between high aspect ratio metal lines at tight pitches, to reduce the capacitance between the metal lines. A deposition process for a dielectric material between metal lines is tuned so that air gaps are formed within the dielectric material, in areas between metal lines. The dielectric material is also deposited between the upper portions of the metal lines, closing the air gaps from the top. The dielectric material is highly selective to a subsequent via etch, so that the dielectric material near the tops of the metal lines acts as an etch stop and prevents punch through into the air gaps.Type: ApplicationFiled: December 26, 2023Publication date: June 26, 2025Applicant: Intel CorporationInventors: Ananya Dutta, Akshit Peer, Ryan Pearce, Sreenivas Kosaraju, Ece Alat, Sudipto Naskar, Jeffery Bielefeld, Mauro J. Kobrinsky
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Patent number: 12342551Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.Type: GrantFiled: January 2, 2024Date of Patent: June 24, 2025Assignee: Intel CorporationInventors: Sudipto Naskar, Manish Chandhok, Abhishek A. Sharma, Roman Caudillo, Scott B. Clendenning, Cheyun Lin
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Publication number: 20250120100Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 2, 2024Publication date: April 10, 2025Inventors: Sudipto NASKAR, Manish CHANDHOK, Abhishek A. SHARMA, Roman CAUDILLO, Scott B. CLENDENNING, Cheyun LIN
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Publication number: 20250112037Abstract: Selective dielectric growth directing contact to gate or contact to trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures and have an uppermost surface above an uppermost surface of gate electrodes of the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures. A dielectric-on-metal (DOM) layer is on and is confined to the uppermost surface of the conductive trench contact structures. A gate contact via is on a gate electrode of one of the plurality of gate structures.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Inventors: Mark KOEPER, Andrew MOORE, Sreenivas KOSARAJU, Nicholas J. KYBERT, Mengcheng LU, Atul MADHAVAN, Sudipto NASKAR, Wei Z. QIU, Tiffany R. ZINK
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Publication number: 20250113581Abstract: Trench contact structures with airgap spacers, and methods of fabricating trench contact structures with airgap spacers, are described. In an example, an integrated circuit structure includes a fin structure or a nanowire structure. An epitaxial source or drain structure is on the fin structure or the nanowire structure. A gate structure is over the fin structure or around the nanowire structure. A trench contact structure is laterally spaced apart from the gate structure and coupled to the epitaxial source or drain structure. A trench contact spacer is adjacent to sidewalls of the trench contact structure, the trench contact spacer including an outer spacer portion, an airgap, and an inner spacer portion.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Inventors: Hwichan JUN, Guillaume BOUCHE, Sudipto NASKAR
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Publication number: 20250105148Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines on a same level and along a same direction, a first one of the plurality of conductive lines having a first width and a first composition, and a second one of the plurality of conductive lines having a second width and a second composition. The second width greater than the first width, and the second composition is different than the first composition. The second one of the plurality of conductive lines has an uppermost surface above an uppermost surface of the first one of the plurality of conductive lines.Type: ApplicationFiled: September 26, 2023Publication date: March 27, 2025Inventors: Marvin PAIK, June CHOI, Shao Ming KOH, Supanee SUKRITTANON, Ananya DUTTA, Sudipto NASKAR
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Publication number: 20250098242Abstract: IC structures with air gap insulation in place of gate spacers are disclosed. An example IC structure includes a transistor comprising a channel region and a source or drain (S/D) region, a gate structure coupled to the channel region and comprising a gate electrode material and a first electrically conductive material, a S/D contact structure coupled to the S/D region and comprising a second electrically conductive material, a gap between the gate structure and the S/D contact structure, and a liner material on at least a portion of a sidewall of the gap, the liner material comprising aluminum and oxygen.Type: ApplicationFiled: September 15, 2023Publication date: March 20, 2025Applicant: Intel CorporationInventors: Seda Cekli, Makram Abd El Qader, Sudipto Naskar, Anh Phan, Rishabh Mehandru
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Patent number: 12249577Abstract: An integrated circuit structure includes a first interconnect level including a first dielectric between a pair of interconnect structures, a second interconnect level above the first interconnect level. The second interconnect level includes a cap structure including a second dielectric on the first dielectric, the cap structure includes a top surface and a sidewall surface and a liner comprising a third dielectric on the top surface and on the sidewall surface.Type: GrantFiled: December 17, 2020Date of Patent: March 11, 2025Assignee: Intel CorporationInventors: Shashi Vyas, Sudipto Naskar, Charles Wallace
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Publication number: 20250006812Abstract: N-type gate-all-around (nanosheet, nanoribbon, nanowire) field-effect transistors (GAAFETs) vertically stacked on top of p-type GAAFETs in complementary FET (CFET) devices comprise non-crystalline silicon layers that form the n-type transistor source, drain, and channel regions. The non-crystalline silicon layers can be formed via deposition, which can provide for a simplified processing flow to form the middle dielectric layer between the n-type and p-type GAAFETs relative to processing flows where the silicon layers forming the n-type transistor source, drain, and channel regions are grown epitaxially.Type: ApplicationFiled: June 30, 2023Publication date: January 2, 2025Applicant: INTEL CORPORATIONInventors: Sudipto Naskar, Sukru Yemenicioglu, Abhishek Anil Sharma, Van Le, Weimin Han
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Patent number: 12176408Abstract: A transistor includes a first channel layer over a second channel layer, an epitaxial source structure coupled to a first end of the first and second channel layers and an epitaxial drain structure coupled to a second end of the first and second channel layers. The transistor includes a gate between the epitaxial source structure and the epitaxial drain structure, where the gate is above the first channel layer and between the first channel layer and the second channel layer. The transistor includes a first spacer of a first material, between the first and second channel layers includes. The first spacer has at least one convex sidewall that is between the gate and the epitaxial source structure and between the gate and the epitaxial drain structure. The transistor also includes a second spacer of a second material having substantially vertical sidewalls above the first channel layer.Type: GrantFiled: December 22, 2020Date of Patent: December 24, 2024Assignee: Intel CorporationInventors: Sudipto Naskar, Willy Rachmady, Hsin-Fen Li, Christopher Parker, Prashant Wadhwa, Tahir Ghani, Mohammad Hasan, Jianqiang Lin
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Publication number: 20240421181Abstract: Disclosed herein are IC devices with 3D interlocked corrugated capacitor structures. An example IC device includes a support structure (e.g., a substrate, a die, a wafer, or a chip), an insulator material over the support structure, and a first and a second corrugated capacitor structures extending into the insulator material, where a projection of at least one of the protrusions of the first corrugated capacitor structure onto a plane parallel to the support structure overlaps with a projection of at least one of the protrusions of the second corrugated capacitor structure onto the plane.Type: ApplicationFiled: June 13, 2023Publication date: December 19, 2024Applicant: Intel CorporationInventors: Denzil Frost, Sudipto Naskar
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Publication number: 20240332285Abstract: An integrated circuit device comprising a resistor formed on a non-crystalline substrate, the resistor comprising a gate electrode; a gate dielectric in contact with the gate electrode; a source electrode and a drain electrode; and a thin film transistor TFT channel material coupled between the source electrode and the drain electrode.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Applicant: Intel CorporationInventors: Sukru Yemenicioglu, Abhishek Anil Sharma, Sudipto Naskar, Kalyan C. Kolluru, Chu-Hsin Liang, Bashir Uddin Mahmud, Van Le
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Publication number: 20240332432Abstract: An integrated circuit device comprising a varactor comprising a first conductive contact; a second conductive contact; and a thin film transistor (TFT) channel material coupled between the first conductive contact and the second conductive contact.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Applicant: Intel CorporationInventors: Sukru Yemenicioglu, Abhishek Anil Sharma, Sudipto Naskar, Kalyan C. Kolluru
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Publication number: 20240332299Abstract: An integrated circuit device comprising a plurality of first field effect transistors (FETs) formed on a substrate, wherein a first FET comprises a first channel material comprising a portion of the substrate; and a plurality of second FETs formed on the substrate, wherein a second FET comprises a second channel material that is different from the first channel material, wherein the second channel material comprises a thin film transistor (TFT) channel material.Type: ApplicationFiled: March 29, 2023Publication date: October 3, 2024Applicant: Intel CorporationInventors: Abhishek Anil Sharma, Van Le, Sudipto Naskar, Sukru Yemenicioglu
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Publication number: 20240332166Abstract: Integrated circuit structures having air gaps are described. In an example, an integrated circuit structure includes alternating conductive lines and air gaps above a first dielectric layer. A dielectric structure is between adjacent ones of the conductive lines and over the air gaps. A first etch stop layer is on the dielectric structure but not on the conductive lines. A second etch stop layer is on the first etch stop layer and on the conductive lines. A second dielectric layer is above the second etch stop layer. A conductive via structure is in the second dielectric layer, in the second etch stop layer, and on one of the conductive lines.Type: ApplicationFiled: April 2, 2023Publication date: October 3, 2024Inventors: Seda CEKLI, Sudipto NASKAR, Ananya DUTTA, Supanee SUKRITTANON, Akshit PEER, Navneethakrishnan SALIVATI, Jeffery BIELEFELD, Makram ABD EL QADER, Mauro J. KOBRINSKY, Sachin VAIDYA
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Publication number: 20240332290Abstract: Transistor structures comprising a gate electrode, or “gate,” that is self-aligned to underlying channel material. A mask material employed for patterning the channel material is further employed to define a cap of mask material having a larger width that protects a portion of gate material during a gate etch. The cap is therefore self-aligned to the channel material so that an amount by which a gate material extends laterally beyond the channel material is ensured to be symmetrical about a centerline of the channel material.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Applicant: Intel CorporationInventors: Shao-Ming Koh, Patrick Morrow, Nikhil Mehta, Leonard Guler, Sudipto Naskar, Alison Davis, Dan Lavric, Matthew Prince, Jeanne Luce, Charles Wallace, Cortnie Vogelsberg, Rajaram Pai, Caitlin Kilroy, Jojo Amonoo, Sean Pursel, Yulia Gotlib
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Publication number: 20240324167Abstract: A high performance (HP) thin film transistor (TFT) architecture to enable fabricating backside memory after metallization starts, or as part of back end of line (BEOL) processes. The HP TFT material is suitable for fabricating the memory stack at the lower BEOL temperatures while still delivering the switching speed requirements of a 3D memory stack in the CIM component. A through silicon via (TSV) architecture connects the logic and the memory in the die.Type: ApplicationFiled: March 24, 2023Publication date: September 26, 2024Applicant: Intel CorporationInventors: Sudipto Naskar, Abhishek Anil Sharma, Sukru Yemenicioglu, Weimin Han, Van Le