Abstract: Devices, transistor structures, systems, and techniques are described herein related to gate all around field effect transistors having a stack of nanowires (i.e., semiconductor structures) contacted by epitaxial source and drain structures at opposite ends of the nanowires. The transistors include a gate structure vertically between the nanowires. Spacer structures of silicon germanium oxide separate the ends of the nanowires spacer and separate the source and drains structures from the gate structure.

Abstract: Integrated circuit (IC) devices having dielectric material separating adjacent source and drain bodies. An IC device may include adjacent first and second transistor structures having adjacent source or drain bodies separated by a dielectric material on first and second sidewalls of a first of the source or drain bodies (but only on the sidewall of the second source or drain body adjacent the first source or drain body). An isolation structure of a second dielectric material may be on the first dielectric material, on the first and second source or drain bodies, and between first and second contact structures on the first and second source or drain bodies. The dielectric material on first and second sidewalls of the first source or drain body may be selectively deposited (e.g., conformally) before the second source or drain body is grown.

Abstract: Heat sink incorporation in integrated circuit layers using high accuracy bonding is described. In an example, an integrated circuit structure includes a first device layer. A second device layer is below the first device layer. An interconnect structure is between the first device layer and the second device layer. A heat sink material layer is between the interconnect structure and the second device layer.

Abstract: Device stacking in integrated circuit layers using high accuracy bonding is described. In an example, an integrated circuit structure includes a first device layer above a first interconnect structure, the first device layer including nanowire-based transistors or fin-based transistors. The integrated circuit structure includes a second device layer below a second interconnect structure, the second device layer including nanowire-based transistors or fin-based transistors, and the second interconnect structure bonded directly to the first interconnect structure.

Abstract: Disclosed herein are IC devices with 3D interlocked corrugated capacitor structures. An example IC device includes a support structure (e.g., a substrate, a die, a wafer, or a chip), an insulator material over the support structure, and a first and a second corrugated capacitor structures extending into the insulator material, where a projection of at least one of the protrusions of the first corrugated capacitor structure onto a plane parallel to the support structure overlaps with a projection of at least one of the protrusions of the second corrugated capacitor structure onto the plane.

Abstract: Techniques are provided herein to form semiconductor devices that include forksheet transistors with a self-aligned dielectric spine having an airgap. The airgap may constitute a majority of the total volume of the dielectric spine, this lowering the dielectric constant of the dielectric spine and decreasing parasitic capacitance. In an example, first and second semiconductor devices have first and second semiconductor regions, respectively, extending in a first direction between corresponding source and drain regions. The first and second semiconductor regions may include any number of nanosheets. A dielectric spine extends in the first direction between the first and second semiconductor regions. The dielectric spine includes a dielectric liner adjacent to the sides of the first and second semiconductor regions. A remaining volume of the dielectric spine at least partially bound by the dielectric liner includes an airgap. A dielectric cap structure may be included over the airgap.

Abstract: Techniques are provided herein to form an integrated circuit having semiconductor devices with low-k inner dielectric spacers between semiconductor bodies (e.g., nanoribbons, nanowires, or nanosheets). The dielectric spacers may include any suitable low-k dielectric material. Additionally, the inner dielectric spacers may be formed after the formation of source or drain regions, which improves the stress profile of the source or drain regions against the semiconductor bodies. In one such example, semiconductor bodies extend in a first direction between source or drain regions and a gate structure extends in a second direction over the semiconductor bodies between the source or drain regions. Inner spacers separate the gate structure from the source or drain regions along the first direction. The inner spacers may include a low-k dielectric material, such as silicon dioxide. In some examples, the inner spacers extend outwards beyond the ends of the semiconductor bodies along the first direction.

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer over a conductive interconnect line, the ILD layer having a trench therein, the trench exposing a portion of the conductive interconnect line. A dielectric liner layer is along a top surface of the ILD layer and along sidewalls of the trench, the dielectric liner layer having an opening therein, the opening over the portion of the conductive interconnect line. A conductive via structure is in the trench and between portions of the dielectric liner layer along the sidewalls of the trench, the conductive via structure having a portion extending vertically beneath the dielectric liner layer and in contact with the portion of the conductive interconnect line.

Abstract: Technologies for air gaps in semiconductor dies with aluminum oxide liners are disclosed. In an illustrative embodiment, high-aspect-ratio traces on an interconnect layer of a semiconductor die have a relatively narrow pitch. In order to reduce the capacitance between neighboring traces, an air gap is present. A liner above the air gap prevents the air gap from being filled during the semiconductor processing. In an illustrative embodiment, the liner is aluminum oxide, which may prevent stress induced leakage current (SILC) that may result when using silicon oxide or other materials.

Abstract: Capacitors that include an amorphous insulator layer can provide high capacitance density and low leakage. A capacitor may include two metal plates, a crystalline insulator material between the metal plates, and a thin layer of an amorphous insulator within the crystalline layer. The crystalline insulator material may be crystalline titanium dioxide, such as rutile, or a dielectric perovskite oxide, such as strontium titanium oxide or barium titanium oxide. The amorphous layer may be an amorphous oxide, such as amorphous titanium oxide, or a different oxide from the crystalline layer. The amorphous oxide layer may be sandwiched between two layers of the crystalline insulator. Alternatively, the amorphous oxide layer may be adjacent to one of the metal plates. The capacitors may be used in decoupling capacitors, memory, or for other applications.

Abstract: Disclosed herein are integrated circuit (IC) structures fabricated with techniques to reduce a gated subfin region in nanoribbon-based transistors. In one example, the technique involves depositing a film over the shallow trench insulator (STI) between adjacent subfins, where the film has a different material composition than the STI. In accordance with examples described herein, the film over the STI can protect the STI during various etch and clean processes to minimize unintentional recession of the STI and thus minimize the presence of gated subfins in the final IC structure. In some examples, the film may be present over the STI in the final IC structure in a plane with source or drain contact structures, and may also be present over the STI in a metal gate region.

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cuts plugged with air gap structures are described. For example, an integrated circuit structure includes an insulating structure laterally between a first gate structure and a second gate structure, where the insulating structure extends from a level above to a level below a first vertical stack of horizontal nanowires or fin and a second stack of horizontal nanowires or fin. The insulating structure includes a dielectric liner, a cavity within the dielectric liner, and a dielectric cap over the cavity. The dielectric liner is in contact with the first gate electrode and the second gate electrode.

Abstract: Integrated circuit structures having contacts for uniform grid metal gate and trench contact cut are described. A structure includes a dielectric sidewall spacer between a gate electrode and a conductive trench contact. A dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A dielectric cap layer covers the dielectric sidewall spacer and the dielectric cut plug structure, and exposes a portion of the gate electrode and a portion of the conductive trench contact. A conductive via is in contact with the portion of the gate electrode or the portion of the conductive trench contact. The conductive via overlaps a top surface of the dielectric cap layer.

Abstract: Integrated circuit structures having direct backside source or drain contacts are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins, and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the epitaxial source or drain structure over and electrically coupled to a corresponding conductive backside contact that extends laterally beyond the epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

Abstract: A thin-film transistor has a channel region with multiple thin-film layers. The transistor has a gate at one side (e.g., at the bottom) and two source/drain contacts on the opposite side (e.g., at the top). One or more channel layers closer to the gate (e.g., lower channel layers) have a higher mobility than one or more channel layers farther from the gate (e.g., upper channel layers). Reducing mobility near the top of the device increases stability of the channel during additional processing.

Abstract: An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.

Abstract: Techniques are provided to form semiconductor devices that include an epitaxial contact with an airgap spacer surrounding a portion of the contact. Accordingly, the airgap spacer is between the contact and an adjacent gate structure and is between the contact and an adjacent dielectric structure. A semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region) that extends from a first source or drain region to a second source or drain region. A dielectric structure may extend through an entire thickness of the gate structure and along the first direction to also be adjacent to the first and second source or drain regions. Conductive conducts are formed on one or both of the first source or drain region and the second source or drain region. An airgap spacer wraps around the entire perimeter of at least one of the conductive contacts.

Abstract: Techniques are provided herein to form semiconductor devices having different gate lengths on the same die. In an example, any number of first semiconductor devices includes first gate structures around first semiconductor regions and any number of second semiconductor devices include second gate structures around second semiconductor regions. The first gate structures have a first gate length around the first semiconductor regions and the second gate structures have a second gate length around the second semiconductor regions with the second gate length being greater than the first gate length. An upper thickness of each the first and second gate structures may be the same, despite the gate length diversity. The first semiconductor devices include first inner spacer structures around ends of the first semiconductor regions that have a greater lateral thickness compared to second inner spacer structures around ends of the second semiconductor regions of the second semiconductor devices.

Abstract: An integrated circuit device includes (i) a first interconnect feature extending within a first dielectric material, and (ii) a second interconnect feature extending within the first dielectric material, and landing on the first interconnect feature. The integrated circuit device further includes a layer having a first section and a second section, wherein the layer includes a second dielectric material that is compositionally different from the first dielectric material. An opening between the first section and the second section is above, and vertically aligned to, the first interconnect feature. The second interconnect feature extends through the opening. In an example, each of the first section and the second section is vertically separated from the first interconnect feature by at least 2 nanometers (nm). In an example, a dielectric constant of the second dielectric material is higher than a dielectric constant of the first dielectric material by at least 5%.

Abstract: Integrated circuit (IC) devices with non-planar transistors may be formed from a material stack having a sacrificial layer between one or more mask material layers and a top surface of a channel material. An IC device may include a non-planar transistor with a gate spacer layer having portions with a same or consistent composition, both over an upper surface of the channel material and under a lower surface of the channel material. The gate spacer layer may have a different composition than a gate endcap spacer layer.