Patents by Inventor Sudipto Ranendra Roy

Sudipto Ranendra Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6987321
    Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: January 17, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subbash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
  • Publication number: 20050112799
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Application
    Filed: November 15, 2004
    Publication date: May 26, 2005
    Inventors: Simon Chooi, Yakub Aliyu, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Ho, Yi Xu
  • Patent number: 6821888
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: November 23, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yakub Aliyu, Simon Chooi, Meisheng Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Publication number: 20040227247
    Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.
    Type: Application
    Filed: November 21, 2003
    Publication date: November 18, 2004
    Applicant: CHARTERED SEMICONDUCTOR MANFACTURING LTD.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subbash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
  • Patent number: 6813796
    Abstract: A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: November 9, 2004
    Assignee: Chartered Semiconductor
    Inventors: Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho
  • Patent number: 6720204
    Abstract: A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: April 13, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: John Leonard Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
  • Patent number: 6705512
    Abstract: A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: March 16, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Patent number: 6692579
    Abstract: A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: February 17, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Sudipto Ranendra Roy, Yi Xu, Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho, Subhash Gupta
  • Patent number: 6683002
    Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: January 27, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
  • Patent number: 6670209
    Abstract: A process for forming a planarized metal layer by forming the plug and overlying metal interconnect simultaneously in order to maintain a uniform gap between the passivation layer of a bottom substrate and the top substrate of a LCD integrated circuit device is described. Semiconductor device structures in and on a semiconductor substrate wherein the semiconductor device structures are covered by an insulating layer. A trench is patterned into the insulating layer and a via opening is made within the trench through the insulating layer to one of the underlying semiconductor device structures. A metal layer is deposited overlying the insulating layer and within the trench and via opening. The metal layer overlying insulating layer is polished away leaving the metal layer within the trench to form a metal pixel and within the via opening to form an interconnect between the metal pixel and the underlying semiconductor device wherein the top surface of the substrate is planarized.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: December 30, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventor: Sudipto Ranendra Roy
  • Publication number: 20030192943
    Abstract: A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.
    Type: Application
    Filed: April 11, 2002
    Publication date: October 16, 2003
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: John Leonard Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
  • Publication number: 20030140943
    Abstract: A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.
    Type: Application
    Filed: February 3, 2003
    Publication date: July 31, 2003
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho
  • Patent number: 6547652
    Abstract: An apparatus for multiple component slurry distribution during semiconductor wafer polishing operations. Concurrent polishing pad conditioning is obtained by means of a novel polishing pad design where polishing pads are mounted in a cylindrical configuration as opposed to the conventional flat surface configuration. A polishing pad conditioner is provided to refurbish the polishing pad.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: April 15, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventor: Sudipto Ranendra Roy
  • Patent number: 6540841
    Abstract: A new method and apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: April 1, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho
  • Patent number: 6521079
    Abstract: An apparatus for closed loop slurry distribution during semiconductor wafer polishing operations. The traditional peristaltic pump for slurry supply is eliminated thus eliminating irregularities in the conventional slurry supply. Common platform mounting of the slurry reservoir and the polishing apparatus resulting in concurrent and identical motion of the slurry supply reservoir and the polishing apparatus. The polishing medium is mounted on the outside of a cylinder as opposed to the conventional table mounting, the polishing medium rotates around the axis of the cylinder on which this polishing medium is mounted. The polishing pads are in direct physical contact with the slurry supply without the intervention of any slurry pumping arrangement.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: February 18, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventor: Sudipto Ranendra Roy
  • Publication number: 20030032275
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Application
    Filed: February 13, 2002
    Publication date: February 13, 2003
    Inventors: Yakub Aliyu, Simon Chooi, Meisheng Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Patent number: 6475810
    Abstract: A new method of forming a dual damascene interconnect structure, wherein damage of interconnect and contamination of dielectrics during etching is minimized by having an embedded organic stop layer over the lower interconnect and later etching the organic stop layer with an H2 containing plasma, or hydrogen radical.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: November 5, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu, Simon Chooi, Yakub Aliyu
  • Patent number: 6429117
    Abstract: A method of preventing metal penetration and diffusion from metal structures formed over a semiconductor structure, comprising the following steps. A semiconductor structure including a patterned dielectric layer is provided. The patterned dielectric layer includes an opening and an upper surface. The dielectric layer surface is then passivated to form a passivation layer. A metal plug is formed within the dielectric layer opening. The passivation layer prevents penetration and diffusion of metal out from the metal plug into the semiconductor structure and the patterned dielectric layer.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: August 6, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: John Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
  • Publication number: 20020100794
    Abstract: A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.
    Type: Application
    Filed: March 15, 2002
    Publication date: August 1, 2002
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Publication number: 20020096190
    Abstract: A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity.
    Type: Application
    Filed: January 19, 2001
    Publication date: July 25, 2002
    Applicant: Chartered Semiconductor Manufacturing Inc.
    Inventors: Sudipto Ranendra Roy, Yi Xu, Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho, Subhash Gupta