Patents by Inventor Sue Crank

Sue Crank has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7511350
    Abstract: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: March 31, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Peijun J. Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas D. Bonifield, Homi Mogul
  • Publication number: 20080128837
    Abstract: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
    Type: Application
    Filed: January 23, 2008
    Publication date: June 5, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Peijun J. Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas D. Bonifield, Homi Mogul
  • Patent number: 7344985
    Abstract: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: March 18, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Peijun J. Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas D. Bonifield, Homi Mogul
  • Publication number: 20070141840
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.
    Type: Application
    Filed: February 26, 2007
    Publication date: June 21, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Peijun Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas Bonifield, Homi Mogul
  • Patent number: 7211516
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: May 1, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Peijun J. Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas D. Bonifield, Homi Mogul
  • Publication number: 20070049022
    Abstract: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
    Type: Application
    Filed: October 20, 2006
    Publication date: March 1, 2007
    Applicant: Texas Instruments, Incorporated
    Inventors: Peijun Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas Bonifield, Homi Mogul
  • Publication number: 20060223295
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.
    Type: Application
    Filed: April 1, 2005
    Publication date: October 5, 2006
    Applicant: Texas Instruments, Incorporated
    Inventors: Peijun Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas Bonifield, Homi Mogul
  • Publication number: 20060035463
    Abstract: A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to about 15 angstroms thick. In various embodiments, treating exposed silicon to form an oxide comprises forming a non- thermal oxide. Treating exposed silicon to form an oxide may also comprise treating the exposed silicon with an oxidizing plasma; alternatively, treating exposed silicon to form an oxide may comprise forming a chemical oxide. In certain other embodiments, treating exposed silicon to form an oxide comprises treating exposed silicon with a solution comprising ammonium hydroxide, hydrogen peroxide, and water; hydrochloric acid, hydrogen peroxide, and water; hydrogen peroxide; ozone; ozonated deionized water; or combinations thereof.
    Type: Application
    Filed: August 10, 2004
    Publication date: February 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Sue Crank, Shirin Siddiqui, Deborah Riley, Trace Hurd, Peijun Chen
  • Publication number: 20060024935
    Abstract: The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises implanting small atoms into an nMOS semiconductor substrate (130) to a depth (132) no greater than about 30 nanometers into the nMOS semiconductor substrate. The method further comprises depositing a transition metal layer (400) over the nMOS semiconductor substrate. The transition metal layer and the nMOS semiconductor substrate are reacted to form the metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (700).
    Type: Application
    Filed: July 30, 2004
    Publication date: February 2, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Duofeng Yue, Peijun Chen, Sue Crank, Thomas Bonifield, Jiong-Ping Lu, Jie-Jie Xu
  • Publication number: 20060019478
    Abstract: A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.
    Type: Application
    Filed: July 21, 2004
    Publication date: January 26, 2006
    Inventors: Song Zhao, Sue Crank, Amitava Chatterjee, Kaiping Liu, Jiong-Ping Lu, Donald Miles, Duofeng Yue, Lance Robertson