Patents by Inventor Sue E. Crank

Sue E. Crank has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7355255
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: April 8, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Peijun J. Chen, Duofeng Yue, Amitabh Jain, Sue E. Crank, Thomas D. Bonifield, Homi C. Mogul
  • Patent number: 7029967
    Abstract: A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Song Zhao, Sue E. Crank, Amitava Chatterjee, Kaiping Liu, Jiong-Ping Lu, Donald S. Miles, Duofeng Yue, Lance S. Robertson
  • Patent number: 5316974
    Abstract: An improved metallized structure (10) is formed from a copper seed layer (46) and a copper structure (48). Semiconductor devices to be connected (16-18) are covered by a conductive barrier layer (20). An oxide layer (28) is then deposited over the barrier layer (20) and patterned using standard photolithographic techniques and an anisotropic plasma etch. Vertical sidewalls (36-38) are formed by the etch and an HF deglaze. A seed layer (44-46) is then sputtered onto a photoresist layer (30) and the exposed barrier layer (20). After stripping the photoresist (30) and the seed layer (44) thereon, the copper structure (48) is electroplated over the remaining seed layer (46). The structure (48) thus formed has approximately vertical sidewalls (24-26) for improved contact with subsequent layers.
    Type: Grant
    Filed: April 30, 1990
    Date of Patent: May 31, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Sue E. Crank
  • Patent number: 4874723
    Abstract: A thin film etching process, wherein the rate of deposition of a robust sidewall passivant is controlled so that passivants can be continually deposited on the sidewalls of the resist pattern to change the geometry of the resist pattern during the processing step. That is, the existing pattern is modified as if a sidewall filament has been deposited on it, which can be advantageous for many purposes, without the added process complexity required by a sidewall filament process.
    Type: Grant
    Filed: July 16, 1987
    Date of Patent: October 17, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Rhett B. Jucha, Duane E. Carter, Cecil J. Davis, Sue E. Crank
  • Patent number: 4863558
    Abstract: Tungsten is rapidly and anisotropically etched under plasma bombardment conditions by using a feed gas mixture which includes a fluorine source (such as SF.sub.6) plus a bromine source (such as HBr), plus a hydrocarbon source (e.g., an alkyl, such as methane).
    Type: Grant
    Filed: April 27, 1988
    Date of Patent: September 5, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Rhett B. Jucha, Cecil J. Davis, Sue E. Crank
  • Patent number: 4849067
    Abstract: A fluorine based metal etch chemistry, wherein an admixture of etch products (or species which are closely related to etch products) is added during the post etch stage, i.e. during the stage when the pattern has partially cleared by overetch is not yet completed, to maintain the balance of chemistries which provides selectivity and anisotropy. In a tungsten etch, WF.sub.6 is usefully added during the post etch period to provide this loading.
    Type: Grant
    Filed: July 16, 1987
    Date of Patent: July 18, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Rhett B. Jucha, Cecil J. Davis, Duane E. Carter, Sue E. Crank, John I. Jones