Patents by Inventor Sugirtha KRISHNAMURTHY

Sugirtha KRISHNAMURTHY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Robust gate cap for protecting a gate from downstream metallization etch operations
    Patent number: 10916431
    Abstract: Embodiments of the invention describe a method of forming an integrated circuit. The method includes forming an active semiconductor device region over a substrate. A first contact structure is formed over the active semiconductor device region, wherein the first contact structure includes a first contact liner material and a first contact body material. A conductive gate structure is formed over the active semiconductor device region, and a first gate cap material is formed on the conductive gate structure. The first contact liner material includes a first etch selectivity responsive to a first etch composition, the first contact body material includes a second etch selectivity responsive to the first etch composition, and the first gate cap material includes a third etch selectivity responsive to the first etch composition. The first etch selectivity is greater than each of the second and third etch selectivies.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raghuveer Reddy Patlolla, Hari Prasad Amanapu, Vimal Kamineni, Sugirtha Krishnamurthy, Viraj Yashawant Sardesai, Cornelius Brown Peethala
  • ROBUST GATE CAP FOR PROTECTING A GATE FROM DOWNSTREAM METALLIZATION ETCH OPERATIONS
    Publication number: 20200335345
    Abstract: Embodiments of the invention describe a method of forming an integrated circuit. The method includes forming an active semiconductor device region over a substrate. A first contact structure is formed over the active semiconductor device region, wherein the first contact structure includes a first contact liner material and a first contact body material. A conductive gate structure is formed over the active semiconductor device region, and a first gate cap material is formed on the conductive gate structure. The first contact liner material includes a first etch selectivity responsive to a first etch composition, the first contact body material includes a second etch selectivity responsive to the first etch composition, and the first gate cap material includes a third etch selectivity responsive to the first etch composition. The first etch selectivity is greater than each of the second and third etch selectivies.
    Type: Application
    Filed: April 16, 2019
    Publication date: October 22, 2020
    Inventors: Raghuveer Reddy Patlolla, Hari Prasad Amanapu, Vimal Kamineni, Sugirtha Krishnamurthy, Viraj Yashawant Sardesai, Cornelius Brown Peethala
  • GATE SKIRT OXIDATION FOR IMPROVED FINFET PERFORMANCE AND METHOD FOR PRODUCING THE SAME
    Publication number: 20190305105
    Abstract: A method for controlling the gate length within a FinFET device to increase power performance and the resulting device are provided. Embodiments include forming a vertical gate to extend over a plurality of fins; depositing a respective oxide layer over each of a plurality of skirt regions formed at respective points of intersection of the vertical gate with the plurality of fins; and oxidizing each oxide layer to form a plurality of oxidized gate skirts.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Qun GAO, Christopher NASSAR, Sugirtha KRISHNAMURTHY, Domingo Antonio FERRER LUPPI, John SPORRE, Shahab SIDDIQUI, Beth BAUMERT, Abu ZAINUDDIN, Jinping LIU, Tae Jeong LEE, Luigi PANTISANO, Heather LAZAR, Hui ZANG