Patents by Inventor Suguru HONDO
Suguru HONDO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10096489Abstract: Provided is a method for manufacturing a semiconductor device with favorable electrical characteristics. The following steps are performed in the following order: forming an oxide semiconductor film over a substrate having a substantially planar surface; selectively etching the oxide semiconductor film to form an oxide semiconductor layer; implanting an oxygen ion on a top surface of the oxide semiconductor layer and a side surface of the oxide semiconductor layer in a cross-section perpendicular to the substantially planar surface in a channel width direction of the oxide semiconductor layer from an angle 0°<?<90°; forming an insulating layer over the oxide semiconductor layer, and performing heat treatment on the oxide semiconductor layer to diffuse oxygen into the oxide semiconductor layer.Type: GrantFiled: March 2, 2015Date of Patent: October 9, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Suguru Hondo, Naoto Yamade
-
Patent number: 9947794Abstract: A semiconductor device that operates at high speed. A semiconductor device with favorable switching characteristics. A highly integrated semiconductor device. A miniaturized semiconductor device. The semiconductor device is formed by: fainting a semiconductor film including an opening, on an insulating surface; forming a conductive film over the semiconductor film and in the opening, and removing the conductive film over the semiconductor film to form a conductive pillar in the opening; forming an island-shaped mask over the conductive pillar and the semiconductor film; etching the conductive pillar and the semiconductor film using the mask to form a first electrode and a first semiconductor; forming a gate insulating film on a top surface and a side surface of the first semiconductor; and forming a gate electrode that is in contact with a top surface of the gate insulating film and faces the top surface and the side surface of the first semiconductor.Type: GrantFiled: February 15, 2017Date of Patent: April 17, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Kazuya Hanaoka, Suguru Hondo, Shunpei Yamazaki
-
Patent number: 9899533Abstract: A transistor including an oxide semiconductor and having favorable operation characteristics is provided. Further, by using the transistor, a semiconductor having improved operation characteristics can be provided. In planar view, one of a source electrode and a drain electrode of the transistor is surrounded by a ring-shaped gate electrode. Further, in planar view, one of the source electrode and the drain electrode of the transistor is surrounded by a channel formation region. Accordingly, the source electrode is not electrically connected to the drain electrode through a parasitic channel generated in an end portion of an island-shaped oxide semiconductor layer.Type: GrantFiled: July 14, 2015Date of Patent: February 20, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Atsuo Isobe, Yuki Hata, Suguru Hondo
-
Patent number: 9837551Abstract: Provided is a semiconductor device that can be miniaturized in a simple process and that can prevent deterioration of electrical characteristics due to miniaturization. The semiconductor device includes an oxide semiconductor layer, a first conductor in contact with the oxide semiconductor layer, and an insulator in contact with the first conductor. Further, an opening portion is provided in the oxide semiconductor layer, the first conductor, and the insulator. In the opening portion, side surfaces of the oxide semiconductor layer, the first conductor, and the insulator are aligned, and the oxide semiconductor layer and the first conductor are electrically connected to a second conductor by side contact.Type: GrantFiled: April 22, 2014Date of Patent: December 5, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Suguru Hondo, Kazuya Hanaoka, Shinya Sasagawa, Naoto Kusumoto
-
Patent number: 9773915Abstract: A semiconductor device using oxide semiconductor with favorable electrical characteristics, or a highly reliable semiconductor device is provided. A semiconductor device is manufactured by: forming an oxide semiconductor layer over an insulating surface; forming source and drain electrodes over the oxide semiconductor layer; forming an insulating film and a conductive film in this order over the oxide semiconductor layer and the source and drain electrodes; etching part of the conductive film and insulating film to form a gate electrode and a gate insulating layer, and etching part of the upper portions of the source and drain electrodes to form a first covering layer containing a constituent element of the source and drain electrodes and in contact with the side surface of the gate insulating layer; oxidizing the first covering layer to form a second covering layer; and forming a protective insulating layer containing an oxide over the second covering layer.Type: GrantFiled: June 2, 2014Date of Patent: September 26, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinya Sasagawa, Motomu Kurata, Kazuya Hanaoka, Suguru Hondo
-
Patent number: 9761736Abstract: Provided is a semiconductor device in which a deterioration in electrical characteristics which becomes more noticeable as miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with each side surface of the first oxide semiconductor film and the second oxide semiconductor film; a first insulating film and a second insulating film over the source electrode and the drain electrode; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with an upper surface of the gate insulating film and facing an upper surface and the side surface of the second oxide semiconductor film.Type: GrantFiled: July 22, 2014Date of Patent: September 12, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Shinya Sasagawa, Suguru Hondo, Hideomi Suzawa
-
Patent number: 9685500Abstract: A semiconductor device with a transistor having favorable electrical characteristics is provided. The semiconductor device has a memory circuit and a circuit that are over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. A gate of the first transistor is electrically connected to the capacitor and one of a source and a drain of the second transistor. The circuit includes a third transistor and a fourth transistor that are electrically connected to each other in series. The first transistor and the third transistor each include an active layer including silicon, and the second transistor and the fourth transistor each include an active layer including an oxide semiconductor.Type: GrantFiled: March 12, 2015Date of Patent: June 20, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yutaka Shionoiri, Tomoaki Atsumi, Shuhei Nagatsuka, Yutaka Okazaki, Suguru Hondo
-
Publication number: 20170162687Abstract: A semiconductor device that operates at high speed. A semiconductor device with favorable switching characteristics. A highly integrated semiconductor device. A miniaturized semiconductor device. The semiconductor device is formed by: fainting a semiconductor film including an opening, on an insulating surface; forming a conductive film over the semiconductor film and in the opening, and removing the conductive film over the semiconductor film to form a conductive pillar in the opening; forming an island-shaped mask over the conductive pillar and the semiconductor film; etching the conductive pillar and the semiconductor film using the mask to form a first electrode and a first semiconductor; forming a gate insulating film on a top surface and a side surface of the first semiconductor; and forming a gate electrode that is in contact with a top surface of the gate insulating film and faces the top surface and the side surface of the first semiconductor.Type: ApplicationFiled: February 15, 2017Publication date: June 8, 2017Inventors: Hidekazu MIYAIRI, Kazuya HANAOKA, Suguru HONDO, Shunpei YAMAZAKI
-
Patent number: 9660098Abstract: Stable electrical characteristics and high reliability are provided for a miniaturized semiconductor device including an oxide semiconductor, and the semiconductor device is manufactured. The semiconductor device includes a base insulating layer; an oxide stack which is over the base insulating layer and includes an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide stack; a gate insulating layer over the oxide stack, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer; and an interlayer insulating layer over the gate electrode layer. In the semiconductor device, the defect density in the oxide semiconductor layer is reduced.Type: GrantFiled: October 15, 2015Date of Patent: May 23, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Sachiaki Tezuka, Tetsuhiro Tanaka, Toshihiko Takeuchi, Hideomi Suzawa, Suguru Hondo
-
Patent number: 9590109Abstract: A semiconductor device that operates at high speed. A semiconductor device with favorable switching characteristics. A highly integrated semiconductor device. A miniaturized semiconductor device. The semiconductor device is formed by: forming a semiconductor film including an opening, on an insulating surface; forming a conductive film over the semiconductor film and in the opening, and removing the conductive film over the semiconductor film to form a conductive pillar in the opening; forming an island-shaped mask over the conductive pillar and the semiconductor film; etching the conductive pillar and the semiconductor film using the mask to form a first electrode and a first semiconductor; forming a gate insulating film on a top surface and a side surface of the first semiconductor; and forming a gate electrode that is in contact with a top surface of the gate insulating film and faces the top surface and the side surface of the first semiconductor.Type: GrantFiled: August 19, 2014Date of Patent: March 7, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Kazuya Hanaoka, Suguru Hondo, Shunpei Yamazaki
-
Patent number: 9496138Abstract: In an oxide semiconductor film formed over an insulating surface, an amorphous region remains in the vicinity of the interface with the base, which is thought to cause a variation in the characteristics of a transistor and the like. A base surface or film touching the oxide semiconductor film is formed of a material having a melting point higher than that of a material used for the oxide semiconductor film. Accordingly, a crystalline region is allowed to exist in the vicinity of the interface with the base surface or film touching the oxide semiconductor film. An insulating metal oxide is used for the base surface or film touching the oxide semiconductor film. The metal oxide used here is an aluminum oxide, gallium oxide, or the like that is a material belonging to the same group as the material of the oxide semiconductor film.Type: GrantFiled: June 28, 2012Date of Patent: November 15, 2016Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Masaki Koyama, Kosei Nei, Akihisa Shimomura, Suguru Hondo, Toru Hasegawa
-
Publication number: 20160111546Abstract: Stable electrical characteristics and high reliability are provided for a miniaturized semiconductor device including an oxide semiconductor, and the semiconductor device is manufactured. The semiconductor device includes a base insulating layer; an oxide stack which is over the base insulating layer and includes an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide stack; a gate insulating layer over the oxide stack, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer; and an interlayer insulating layer over the gate electrode layer. In the semiconductor device, the defect density in the oxide semiconductor layer is reduced.Type: ApplicationFiled: October 15, 2015Publication date: April 21, 2016Inventors: Sachiaki TEZUKA, Tetsuhiro TANAKA, Toshihiko TAKEUCHI, Hideomi SUZAWA, Suguru HONDO
-
Patent number: 9293599Abstract: A transistor with stable electric characteristics is provided. A transistor with small variation in electrical characteristics is provided. A miniaturized transistor is provided. A transistor having low off-state current is provided. A transistor having high on-state current is provided. A semiconductor device including the transistor is provided. One embodiment of the present invention is a semiconductor device including an island-shaped stack including a base insulating film and an oxide semiconductor film over the base insulating film; a protective insulating film facing a side surface of the stack and not facing a top surface of the stack; a first conductive film and a second conductive film which are provided over and in contact with the stack to be apart from each other; an insulating film over the stack, the first conductive film, and the second conductive film; and a third conductive film over the insulating film.Type: GrantFiled: May 15, 2014Date of Patent: March 22, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Suguru Hondo, Daigo Ito
-
Patent number: 9276091Abstract: A transistor including an oxide semiconductor film, which has stable electric characteristics is provided. A transistor including an oxide semiconductor film, which has excellent on-state characteristics is also provided. A semiconductor device in which an oxide semiconductor film having low resistance is formed and the resistance of a channel region of the oxide semiconductor film is increased. Note that an oxide semiconductor film is subjected to a process for reducing the resistance to have low resistance. The process for reducing the resistance of the oxide semiconductor film may be a laser process or heat treatment at a temperature higher than or equal to 450° C. and lower than or equal to 740° C., for example. A process for increasing the resistance of the channel region of the oxide semiconductor film having low resistance may be performed by plasma oxidation or implantation of oxygen ions, for example.Type: GrantFiled: April 16, 2015Date of Patent: March 1, 2016Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Suguru Hondo, Akihisa Shimomura, Masaki Koyama, Motomu Kurata, Kazuya Hanaoka, Sho Nagamatsu, Kosei Nei, Toru Hasegawa
-
Publication number: 20150325708Abstract: A transistor capable of being driven at high operating frequency is provided. The transistor includes first to third oxide semiconductor layers, a gate insulating layer, a gate electrode layer, and a portion in which the first to third oxide semiconductor layers are sequentially stacked. Channel length is less than 100 nm, and cutoff frequency at a source-drain voltage of higher than or equal to 1 V and lower than or equal to 2 V is higher than 1 GHz. The gate insulating layer is in contact with a top surface of the third oxide semiconductor layer. The gate electrode layer partly overlaps with the portion with the gate insulating layer positioned therebetween. The second oxide semiconductor layer includes a plurality of c-axis aligned crystal parts and a region in which the concentration of hydrogen measured by secondary ion mass spectrometry is lower than 2×1020 atoms/cm3.Type: ApplicationFiled: May 5, 2015Publication date: November 12, 2015Inventors: Yuto YAKUBO, Suguru HONDO, Akihisa SHIMOMURA, Shunpei YAMAZAKI, Shuhei NAGATSUKA
-
Publication number: 20150318402Abstract: A transistor including an oxide semiconductor and having favorable operation characteristics is provided. Further, by using the transistor, a semiconductor having improved operation characteristics can be provided. In planar view, one of a source electrode and a drain electrode of the transistor is surrounded by a ring-shaped gate electrode. Further, in planar view, one of the source electrode and the drain electrode of the transistor is surrounded by a channel formation region. Accordingly, the source electrode is not electrically connected to the drain electrode through a parasitic channel generated in an end portion of an island-shaped oxide semiconductor layer.Type: ApplicationFiled: July 14, 2015Publication date: November 5, 2015Inventors: Shunpei YAMAZAKI, Atsuo ISOBE, Yuki HATA, Suguru HONDO
-
Patent number: 9166021Abstract: Stable electrical characteristics and high reliability are provided for a miniaturized semiconductor device including an oxide semiconductor, and the semiconductor device is manufactured. The semiconductor device includes a base insulating layer; an oxide stack which is over the base insulating layer and includes an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide stack; a gate insulating layer over the oxide stack, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer; and an interlayer insulating layer over the gate electrode layer. In the semiconductor device, the defect density in the oxide semiconductor layer is reduced.Type: GrantFiled: October 7, 2013Date of Patent: October 20, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Sachiaki Tezuka, Tetsuhiro Tanaka, Toshihiko Takeuchi, Hideomi Suzawa, Suguru Hondo
-
Publication number: 20150263007Abstract: A semiconductor device with a transistor having favorable electrical characteristics is provided. The semiconductor device has a memory circuit and a circuit that are over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. A gate of the first transistor is electrically connected to the capacitor and one of a source and a drain of the second transistor. The circuit includes a third transistor and a fourth transistor that are electrically connected to each other in series. The first transistor and the third transistor each include an active layer including silicon, and the second transistor and the fourth transistor each include an active layer including an oxide semiconductor.Type: ApplicationFiled: March 12, 2015Publication date: September 17, 2015Inventors: Shunpei YAMAZAKI, Yutaka SHIONOIRI, Tomoaki ATSUMI, Shuhei NAGATSUKA, Yutaka OKAZAKI, Suguru HONDO
-
Publication number: 20150255310Abstract: Provided is a method for manufacturing a semiconductor device with favorable electrical characteristics. The following steps are performed in the following order: forming an oxide semiconductor film over a substrate having a substantially planar surface; selectively etching the oxide semiconductor film to form an oxide semiconductor layer; implanting an oxygen ion on a top surface of the oxide semiconductor layer and a side surface of the oxide semiconductor layer in a cross-section perpendicular to the substantially planar surface in a channel width direction of the oxide semiconductor layer from an angle 0°<?<90°; forming an insulating layer over the oxide semiconductor layer, and performing heat treatment on the oxide semiconductor layer to diffuse oxygen into the oxide semiconductor layer.Type: ApplicationFiled: March 2, 2015Publication date: September 10, 2015Inventors: Shunpei YAMAZAKI, Suguru HONDO, Naoto YAMADE
-
Patent number: 9112037Abstract: A transistor including an oxide semiconductor and having favorable operation characteristics is provided. Further, by using the transistor, a semiconductor having improved operation characteristics can be provided. In planar view, one of a source electrode and a drain electrode of the transistor is surrounded by a ring-shaped gate electrode. Further, in planar view, one of the source electrode and the drain electrode of the transistor is surrounded by a channel formation region. Accordingly, the source electrode is not electrically connected to the drain electrode through a parasitic channel generated in an end portion of an island-shaped oxide semiconductor layer.Type: GrantFiled: February 4, 2013Date of Patent: August 18, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Atsuo Isobe, Yuki Hata, Suguru Hondo