Patents by Inventor Suguru KAWASOE
Suguru KAWASOE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942928Abstract: A semiconductor device that outputs a reset signal for controlling a reset operation of a reset target circuit connected to a first power supply and a second power supply having a voltage lower than a voltage of the first power supply, the semiconductor device including: a power supply voltage monitoring circuit connected to the first power supply and the second power supply, the power supply voltage monitoring circuit monitors the voltage of the first power supply, wherein the power supply voltage monitoring circuit includes a first transistor having a first conductive type and a second transistor having a second conductive type different from the first conductive type, and wherein the reset signal is switched when the voltage of the first power supply is equal to or greater than a sum of a threshold voltage of the first transistor, and a threshold voltage of the second transistor.Type: GrantFiled: September 28, 2022Date of Patent: March 26, 2024Assignee: LAPIS TECHNOLOGY CO., LTD.Inventor: Suguru Kawasoe
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Publication number: 20230106646Abstract: A semiconductor device that outputs a reset signal for controlling a reset operation of a reset target circuit connected to a first power supply and a second power supply having a voltage lower than a voltage of the first power supply, the semiconductor device including: a power supply voltage monitoring circuit connected to the first power supply and the second power supply, the power supply voltage monitoring circuit monitors the voltage of the first power supply, wherein the power supply voltage monitoring circuit includes a first transistor having a first conductive type and a second transistor having a second conductive type different from the first conductive type, and wherein the reset signal is switched when the voltage of the first power supply is equal to or greater than a sum of a threshold voltage of the first transistor, and a threshold voltage of the second transistor.Type: ApplicationFiled: September 28, 2022Publication date: April 6, 2023Inventor: SUGURU KAWASOE
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Patent number: 11394355Abstract: A semiconductor device includes: a first buffer at which a predetermined signal is input and that outputs a first output signal; a second buffer at which an inverted signal of the predetermined signal is input and that outputs a second output signal; and a short circuit detection circuit that, in accordance with a potential difference between the first output signal and the second output signal, outputs a short circuit evaluation signal evaluating whether or not there is a ground fault in at least one of a first terminal at an output side of the first buffer or a second terminal at an output side of the second buffer or evaluating whether or not there is a short circuit between the first terminal and the second terminal.Type: GrantFiled: July 28, 2020Date of Patent: July 19, 2022Assignee: LAPIS SEMICONDUCTOR CO., LTD.Inventor: Suguru Kawasoe
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Publication number: 20210036667Abstract: A semiconductor device includes: a first buffer at which a predetermined signal is input and that outputs a first output signal; a second buffer at which an inverted signal of the predetermined signal is input and that outputs a second output signal; and a short circuit detection circuit that, in accordance with a potential difference between the first output signal and the second output signal, outputs a short circuit evaluation signal evaluating whether or not there is a ground fault in at least one of a first terminal at an output side of the first buffer or a second terminal at an output side of the second buffer or evaluating whether or not there is a short circuit between the first terminal and the second terminal.Type: ApplicationFiled: July 28, 2020Publication date: February 4, 2021Applicant: LAPIS Semiconductor Co., Ltd.Inventor: Suguru KAWASOE
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Patent number: 10310579Abstract: A semiconductor integrated circuit capable of efficiently suppressing power consumption when a power supply voltage is lowered is provided.Type: GrantFiled: June 28, 2017Date of Patent: June 4, 2019Assignee: LAPIS Semiconductor Co., Ltd.Inventor: Suguru Kawasoe
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Patent number: 10193337Abstract: A semiconductor device includes: a voltage regulator generating, based on a power supply voltage, an internal power supply voltage having a voltage value lower than that of the power supply voltage and to apply the internal power supply voltage to a power supply line; an internal circuit receiving the internal power supply voltage via the power supply line and a grounding line; and a protection circuit in which first to n-th transistors of PNP type which are Darlington-connected. A collector terminal of each of the first to the n-th transistors is connected to the grounding line. An emitter terminal of the first transistor within the first to the n-th transistors is connected to the power supply line while a base terminal of the n-th transistor within the first to the n-th transistors is connected to the grounding line.Type: GrantFiled: March 25, 2016Date of Patent: January 29, 2019Assignee: LAPIS Semiconductor Co., Ltd.Inventor: Suguru Kawasoe
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Publication number: 20170371389Abstract: A semiconductor integrated circuit capable of efficiently suppressing power consumption when a power supply voltage is lowered is provided.Type: ApplicationFiled: June 28, 2017Publication date: December 28, 2017Applicant: LAPIS Semiconductor Co., Ltd.Inventor: Suguru Kawasoe
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Publication number: 20160285260Abstract: A semiconductor device includes: a voltage regulator generating, based on a power supply voltage, an internal power supply voltage having a voltage value lower than that of the power supply voltage and to apply the internal power supply voltage to a power supply line; an internal circuit receiving the internal power supply voltage via the power supply line and a grounding line; and a protection circuit in which first to n-th transistors of PNP type which are Darlington-connected. A collector terminal of each of the first to the n-th transistors is connected to the grounding line. An emitter terminal of the first transistor within the first to the n-th transistors is connected to the power supply line while a base terminal of the n-th transistor within the first to the n-th transistors is connected to the grounding line.Type: ApplicationFiled: March 25, 2016Publication date: September 29, 2016Applicant: LAPIS Semiconductor Co., Ltd.Inventor: Suguru KAWASOE
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Patent number: 9030264Abstract: A current output control device is provided that includes: a current cell array section including plural current cell circuits that are each connected in parallel between a first terminal (power source) and a second terminal (ground) that connect between the first terminal and the second terminal in by operation ON so as to increase control current flowing between the first terminal and the second terminal; and a code conversion section (decoder) that generates signals (row codes, column codes) to ON/OFF control current cells so as to change the number of current cells that connect the first terminal and the second terminal according to change in an externally input code and that inputs the generated signals to the current cell array section.Type: GrantFiled: May 30, 2013Date of Patent: May 12, 2015Assignee: LAPIS Semiconductor Co., Ltd.Inventor: Suguru Kawasoe
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Patent number: 8619444Abstract: A voltage booster system of a charge pump type includes a regulator for outputting a constant voltage and a charge pump circuit for boosting a voltage of an output terminal of the regulator. The regulator includes a differential amplifier unit for inputting a reference voltage and a feedback voltage according to the voltage of the output terminal, and an output stage portion including an PN connection element having one end portion connected to an application terminal of a power source voltage and another end portion connected to the output terminal. The PN connection element is configured to be controlled according to an output signal of the differential amplifier unit. The charge pump circuit includes a first capacitor to which the voltage of the output terminal is applied to be charged; a second capacitor; a third capacitor; a first switching section; and a second switching section.Type: GrantFiled: April 19, 2012Date of Patent: December 31, 2013Assignee: Lapis Semiconductor Co., Ltd.Inventor: Suguru Kawasoe
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Publication number: 20130328603Abstract: A current output control device is provided that includes: a current cell array section including plural current cell circuits that are each connected in parallel between a first terminal (power source) and a second terminal (ground) that connect between the first terminal and the second terminal in by operation ON so as to increase control current flowing between the first terminal and the second terminal; and a code conversion section (decoder) that generates signals (row codes, column codes) to ON/OFF control current cells so as to change the number of current cells that connect the first terminal and the second terminal according to change in an externally input code and that inputs the generated signals to the current cell array section.Type: ApplicationFiled: May 30, 2013Publication date: December 12, 2013Inventor: Suguru KAWASOE
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Publication number: 20120268096Abstract: A voltage booster system of a charge pump type includes a regulator for outputting a constant voltage and a charge pump circuit for boosting a voltage of an output terminal of the regulator. The regulator includes a differential amplifier unit for inputting a reference voltage and a feedback voltage according to the voltage of the output terminal, and an output stage portion including an PN connection element having one end portion connected to an application terminal of a power source voltage and another end portion connected to the output terminal. The PN connection element is configured to be controlled according to an output signal of the differential amplifier unit. The charge pump circuit includes a first capacitor to which the voltage of the output terminal is applied to be charged; a second capacitor; a third capacitor; a first switching section; and a second switching section.Type: ApplicationFiled: April 19, 2012Publication date: October 25, 2012Inventor: Suguru KAWASOE