Patents by Inventor Suguru Nishikawa
Suguru Nishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096423Abstract: A memory system includes a semiconductor memory that includes a cell unit having a plurality of memory cells, and a control circuit for controlling the plurality of memory cells, and a memory controller configured to control the semiconductor memory. The control circuit is configured to execute a data read operation on the cell unit by using one or more read voltages, acquire first data by the data read operation, generate second data with a data size smaller than the first data, based on the first data, and transmit the second data to the memory controller. The memory controller is configured to determine, based on the second data, whether or not to rewrite the page data written in the cell unit.Type: ApplicationFiled: March 2, 2023Publication date: March 21, 2024Inventors: Dongxiao YU, Masahiro KIYOOKA, Suguru NISHIKAWA, Yoshihisa KOJIMA
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Patent number: 11869596Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.Type: GrantFiled: March 6, 2023Date of Patent: January 9, 2024Assignee: Kioxia CorporationInventors: Suguru Nishikawa, Yoshihisa Kojima, Riki Suzuki, Masanobu Shirakawa, Toshikatsu Hida
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Publication number: 20230420060Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.Type: ApplicationFiled: September 1, 2023Publication date: December 28, 2023Applicant: KIOXIA CORPORATIONInventors: Tomoya KAMATA, Yoshihisa KOJIMA, Suguru NISHIKAWA
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Publication number: 20230342051Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Applicant: KIOXIA CORPORATIONInventors: Shunichi IGAHARA, Toshikatsu HIDA, Riki SUZUKI, Takehiko AMAKI, Suguru NISHIKAWA, Yoshihisa KOJIMA
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Patent number: 11790997Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.Type: GrantFiled: September 10, 2021Date of Patent: October 17, 2023Assignee: Kioxia CorporationInventors: Tomoya Kamata, Yoshihisa Kojima, Suguru Nishikawa
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Patent number: 11789643Abstract: According to one embodiment, a memory system includes non-volatile memory and volatile memory. A controller encodes a first unit size data portion to be written into the non-volatile memory and generates a first error correction code for the data portion, then writes the data portion into the non-volatile memory. The controller also stores the first error correction code in the volatile memory. When non-volatilization of an error correction code protect the data portion is requested, the controller encodes the data portion to generate a second error correction code for the data portion, and then writes the second error correction code into the non-volatile memory. The second error correction code is smaller in size than the first error correction code.Type: GrantFiled: March 2, 2022Date of Patent: October 17, 2023Assignee: Kioxia CorporationInventors: Suguru Nishikawa, Toshikatsu Hida, Shunichi Igahara, Takehiko Amaki
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Publication number: 20230280943Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.Type: ApplicationFiled: May 16, 2023Publication date: September 7, 2023Applicant: Kioxia CorporationInventors: Suguru NISHIKAWA, Yoshihisa KOJIMA, Takehiko AMAKI
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Patent number: 11749350Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.Type: GrantFiled: December 28, 2022Date of Patent: September 5, 2023Assignee: Kioxia CorporationInventors: Suguru Nishikawa, Takehiko Amaki, Yoshihisa Kojima, Shunichi Igahara
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Patent number: 11740965Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.Type: GrantFiled: November 4, 2021Date of Patent: August 29, 2023Assignee: Kioxia CorporationInventors: Shunichi Igahara, Yoshihisa Kojima, Takehiko Amaki, Suguru Nishikawa
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Patent number: 11733888Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.Type: GrantFiled: September 22, 2020Date of Patent: August 22, 2023Assignee: Kioxia CorporationInventors: Shunichi Igahara, Toshikatsu Hida, Riki Suzuki, Takehiko Amaki, Suguru Nishikawa, Yoshihisa Kojima
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Patent number: 11734112Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n?1 data portions of a first unit that are included in n?1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n?1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n?1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.Type: GrantFiled: July 21, 2022Date of Patent: August 22, 2023Assignee: Kioxia CorporationInventors: Takehiko Amaki, Toshikatsu Hida, Shunichi Igahara, Yoshihisa Kojima, Suguru Nishikawa
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Patent number: 11693603Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.Type: GrantFiled: July 6, 2022Date of Patent: July 4, 2023Assignee: KIOXIA CORPORATIONInventors: Suguru Nishikawa, Yoshihisa Kojima, Takehiko Amaki
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Publication number: 20230207016Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Applicant: Kioxia CorporationInventors: Suguru NISHIKAWA, Yoshihisa KOJIMA, Riki SUZUKI, Masanobu SHIRAKAWA, Toshikatsu HIDA
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Patent number: 11657875Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.Type: GrantFiled: June 24, 2022Date of Patent: May 23, 2023Assignee: KIOXIA CORPORATIONInventors: Suguru Nishikawa, Yoshihisa Kojima, Riki Suzuki, Masanobu Shirakawa, Toshikatsu Hida
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Publication number: 20230145598Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.Type: ApplicationFiled: December 28, 2022Publication date: May 11, 2023Applicant: Kioxia CorporationInventors: Suguru NISHIKAWA, Takehiko AMAKI, Yoshihisa KOJIMA, Shunichi IGAHARA
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Publication number: 20230139665Abstract: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.Type: ApplicationFiled: December 30, 2022Publication date: May 4, 2023Inventors: Marie SIA, Yoshihisa KOJIMA, Suguru NISHIKAWA, Riki SUZUKI
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Patent number: 11615851Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.Type: GrantFiled: January 10, 2022Date of Patent: March 28, 2023Assignee: Kioxia CorporationInventors: Suguru Nishikawa, Takehiko Amaki, Yoshihisa Kojima, Shunichi Igahara
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Publication number: 20230073249Abstract: According to one embodiment, a memory system includes non-volatile memory and volatile memory. A controller encodes a first unit size data portion to be written into the non-volatile memory and generates a first error correction code for the data portion, then writes the data portion into the non-volatile memory. The controller also stores the first error correction code in the volatile memory. When non-volatilization of an error correction code protect the data portion is requested, the controller encodes the data portion to generate a second error correction code for the data portion, and then writes the second error correction code into the non-volatile memory. The second error correction code is smaller in size than the first error correction code.Type: ApplicationFiled: March 2, 2022Publication date: March 9, 2023Inventors: Suguru NISHIKAWA, Toshikatsu HIDA, Shunichi IGAHARA, Takehiko AMAKI
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Patent number: 11573740Abstract: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.Type: GrantFiled: July 21, 2021Date of Patent: February 7, 2023Assignee: Kioxia CorporationInventors: Marie Sia, Yoshihisa Kojima, Suguru Nishikawa, Riki Suzuki
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Publication number: 20220358011Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n?1 data portions of a first unit that are included in n?1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n?1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n?1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Applicant: Kioxia CorporationInventors: Takehiko AMAKI, Toshikatsu HIDA, Shunichi IGAHARA, Yoshihisa KOJIMA, Suguru NISHIKAWA