Patents by Inventor Suguru Sakaguchi

Suguru Sakaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200147590
    Abstract: An oxygen reduction catalyst containing as constituent elements cobalt, sulfur, and a transition metal element M being at least one element selected from chromium and molybdenum, the oxygen reduction catalyst being ascertained to have a crystal structure of a cobalt disulfide cubic crystal in powder X-ray diffraction measurement, and having a molar ratio of the transition metal element M to cobalt (M/cobalt) of 5/95 to 15/85. Also disclosed is an electrode having a catalyst layer containing the oxygen reduction catalyst, a membrane electrode assembly including a polymer electrolyte membrane wherein the electrode serves as a cathode and/or an anode, and a fuel cell including the membrane electrode assembly.
    Type: Application
    Filed: December 27, 2017
    Publication date: May 14, 2020
    Applicant: SHOWA DENKO K.K.
    Inventors: Takuya IMAI, Kazuo FURUYA, Kunchan LEE, Suguru SAKAGUCHI, Yoshishige OKUNO
  • Patent number: 10573902
    Abstract: The present invention relates to an oxygen reduction catalyst, an electrode, a membrane electrode assembly, and a fuel cell, and the oxygen reduction catalyst is an oxygen reduction catalyst containing substituted CoS2, in which the substituted CoS2 has a cubic crystal structure, the oxygen reduction catalyst contains the substituted CoS2 within 0.83 nm from the surface thereof, and the substituted CoS2 has at least one substitutional atom selected from the group consisting of Cr, Mo, Mn, Tc, Re, Rh, Cu, and Ag in some of Co atom sites.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: February 25, 2020
    Assignee: SHOWA DENKO K.K.
    Inventors: Suguru Sakaguchi, Yoshishige Okuno, Takuya Imai, Kunchan Lee
  • Publication number: 20190386321
    Abstract: The present invention relates to an oxygen reduction catalyst, an electrode, a membrane electrode assembly, and a fuel cell, and the oxygen reduction catalyst is an oxygen reduction catalyst containing substituted CoS2, in which the substituted CoS2 has a cubic crystal structure, the oxygen reduction catalyst contains the substituted CoS2 within 0.83 nm from the surface thereof, and the substituted CoS2 has at least one substitutional atom selected from the group consisting of Cr, Mo, Mn, Tc, Re, Rh, Cu, and Ag in some of Co atom sites.
    Type: Application
    Filed: December 27, 2017
    Publication date: December 19, 2019
    Applicant: SHOWA DENKO K.K.
    Inventors: Suguru SAKAGUCHI, Yoshishige OKUNO, Takuya IMAI, Kunchan LEE
  • Patent number: 6297074
    Abstract: A film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof wherein a plurality of chip semiconductor devices are laminated onto a substrate. Each chip semiconductor device includes a film carrier tape having leads, a semiconductor chip electrically connected to the leads, a heat sink mounted to a surface of the chip, and a connector for mounting the heat sink, the connector being electrically connected to the leads of the film carrier tape. The film carrier tape includes a carrier member having a metallic layer superposed thereon which is etched so as to form the leads and the heat sink.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: October 2, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Miyano, Koji Serizawa, Hiroyuki Tanaka, Tadao Shinoda, Suguru Sakaguchi
  • Patent number: 6204490
    Abstract: Electronic components are bonded to an electronic circuit board with a lead-free solder. The bonded structure is cooled from a temperature close to the liquids temperature of the solder to a temperature close to the solids temperature of the solder at a first cooling rate of about 10 to 20° C./second, followed by cooling the bonded structure to a temperature lower than the solids temperature of the solder at a second cooling rate of about 0.1 to less than 5° C./second.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: March 20, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Toshiharu Ishida, Tetsuya Nakatsuka, Hanae Shimokawa, Koji Serizawa, Yasuo Amano, Suguru Sakaguchi, Hiroshi Yamaguchi
  • Patent number: 5804872
    Abstract: A film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof wherein a plurality of chip-semiconductor devices are laminated onto a substrate. Each chip semiconductor device includes a film carrier tape having leads, a semiconductor chip electrically connected to the leads, a heat sink mounted to a surface of the chip, and a connector for mounting the heat sink, the connector being electrically connected to the leads of the film carrier tape. The film carrier tape includes a carrier member having a metallic layer superposed thereon which is etched so as to form the leads and the heat sink.
    Type: Grant
    Filed: February 5, 1997
    Date of Patent: September 8, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Miyano, Koji Serizawa, Hiroyuki Tanaka, Tadao Shinoda, Suguru Sakaguchi
  • Patent number: 5631497
    Abstract: A film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof wherein a plurality of chip semiconductor devices are laminated onto a substrate. Each chip semiconductor device includes a film carrier tape having leads, a semiconductor chip electrically connected to the leads, a heat sink mounted to a surface of the chip, and a connector for mounting the heat sink, the connector being electrically connected to the leads of the film carrier tape. The film carrier tape includes a carrier member having a metallic layer superposed thereon which is etched so as to form the leads and the heat sink.
    Type: Grant
    Filed: July 9, 1991
    Date of Patent: May 20, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Miyano, Koji Serizawa, Hiroyuki Tanaka, Tadao Shinoda, Suguru Sakaguchi
  • Patent number: 5440171
    Abstract: In a tape carrier type semiconductor device with reinforcement wherein tape carrier type semiconductor modules are mounted in holes or depressions enclosed by a frame, and at least one flexible circuit is stacked additionally as required, and the semiconductor modules are electrically connected to electrodes formed on the frame, by mounting chip parts such as capacitors on the frame and/or flexible circuit, the mounting area of the semiconductor device can be reduced and the performance can be hyperfunctioned. By stacking a plurality of such semiconductor devices with reinforcement, much more satisfactory effects can be obtained.
    Type: Grant
    Filed: March 8, 1993
    Date of Patent: August 8, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Miyano, Kooji Serizawa, Suguru Sakaguchi, Toshiharu Ishida
  • Patent number: 5421081
    Abstract: A method for producing an electronic part mounting structure in which electronic parts such as IC packages are electrically connected to the surface of a printed circuit board utilizes a low-melting point metal. More particularly, the method provides an electronic part mounting structure capable of sufficiently and assuredly supplying solder to a portion between the terminal of a printed circuit board and the leads of an electric part while maintaining a predetermined thickness required to connect the printed circuit board and the electronic part to each other. By arranging the structure such that a gap, in which a solder layer having a predetermined thickness can be formed between the terminal of the printed circuit board and the lead of the electronic part to be connected to the terminal, is formed, the solder required to solder-connect the two elements can be sufficiently and assuredly supplied to the gap. Therefore, a reliable solder connection can be established.
    Type: Grant
    Filed: May 13, 1993
    Date of Patent: June 6, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Suguru Sakaguchi, Toshiharu Ishida, Kooji Serizawa, Hiroyuki Tanaka, Ichiro Miyano, Hiroshi Nakamura
  • Patent number: 5334875
    Abstract: There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.
    Type: Grant
    Filed: March 2, 1993
    Date of Patent: August 2, 1994
    Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd.
    Inventors: Toshio Sugano, Kohji Nagaoka, Seiichiro Tsukui, Yoshiaki Wakashima, Michio Tanimoto, Masayuki Watanabe, Suguru Sakaguchi, Kunihiko Nishi, Aizo Kaneda, Kohji Serizawa, Michiharu Honda, Tohru Yoshida, Takeshi Komaru, Atsushi Nakamura
  • Patent number: 5219765
    Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device without waste by incorporating predetermined functions into a wafer in a wafer completion process, aging the wafer in a wafer aging process, distinguishing between non-defective and defective chips in a probe inspection process, separating chips in the wafer one by one in a dicing process, sorting out the chips into non-defective and defective chips in a selection process, then analyzing failure information and feeding back the result of the analysis to the wafer completion process in a feedback process, thereby quickly analyzing and repairing a failure process on reliability in the wafer completion process.
    Type: Grant
    Filed: July 6, 1990
    Date of Patent: June 15, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Toru Yoshida, Suguru Sakaguchi, Aizo Kaneda, Kooji Serizawa, Munehisa Kishimoto, Masaaki Mutoh, Kunio Matsumoto, Isao Ohomori, Shingo Yorisaki
  • Patent number: 5198888
    Abstract: There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.
    Type: Grant
    Filed: December 20, 1990
    Date of Patent: March 30, 1993
    Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd.
    Inventors: Toshio Sugano, Kohji Nagaoka, Seiichiro Tsukui, Yoshiaki Wakashima, Michio Tanimoto, Masayuki Watanabe, Suguru Sakaguchi, Kunihiko Nishi, Aizo Kaneda, Kohji Serizawa, Michiharu Honda, Tohru Yoshida, Takeshi Komaru, Atsushi Nakamura
  • Patent number: 5086337
    Abstract: This invention relates to a connecting structure for electrically connecting an electronic part such as an LSI chip to a substrate, its production method and an electronic device using the former. The present invention is particularly useful for connecting electrically a plurality of chips, for which an absorption function of the difference of thermal expansion in a horizontal direction and capability of displacement in a vertical direction are requisite, to a substrate. Moreover, the connecting structure of the present invention can simplify the fabrication process, has high reliability and can be applied to high performance electronic appliances and apparatuses such as electronic computers.
    Type: Grant
    Filed: September 13, 1988
    Date of Patent: February 4, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Takanobu Noro, Kunio Matsumoto, Muneo Oshima, Naoya Kanda, Suguru Sakaguchi, Akira Murata
  • Patent number: 5028986
    Abstract: There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.
    Type: Grant
    Filed: December 23, 1988
    Date of Patent: July 2, 1991
    Assignees: Hitachi, Ltd., HitachiTobu Semiconductor, Ltd.
    Inventors: Toshio Sugano, Kohji Nagaoka, Seiichiro Tsukui, Yoshiaki Wakashima, Michio Tanimoto, Masayuki Watanabe, Suguru Sakaguchi, Kunihiko Nishi, Aizo Kaneda, Kohji Serizawa, Michiharu Honda, Tohru Yoshida, Takeshi Komaru, Atsushi Nakamura
  • Patent number: 4893172
    Abstract: Disclosed is a connecting structure for electrically connecting an electronic part such as an LSI chip to a substrate and a method of manufacturing the same. The present invention is suitable especially for electrical connection between a plurality of chips and a substrate which is required to have a function of absorbing a difference in thermal expansion in the horizontal direction and to deform in the vertical direction, and characterized in that a conductive flat spring having a height not more than the minimum length in the lateral direction is provided between the electronic part such as a chip and a wires substrate.
    Type: Grant
    Filed: January 13, 1988
    Date of Patent: January 9, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Kunio Matsumoto, Muneo Oshima, Suguru Sakaguchi
  • Patent number: 4673772
    Abstract: In connecting an electronic circuit part such as a semiconductor or other part to a substrate for mounting the part with solder, the solder is composed of a high-melting-point solder portion which is subjected to working such as rolling and heat treatment in order to break the cast structure thereof, and a smaller volume of low-melting-point solder portions. The high-melting-point solder portion is connected to both the electronic circuit substrate and the electronic circuit part through the low-point-melting solder portions.This method enables interconnection between objects to be connected without impairing the high ductility and toughness of the high-melting-point solder which is subjected to working and heat treatment. This soldering method ensures highly reliable manufacture of miniaturized high density circuits, such as LSI.
    Type: Grant
    Filed: October 4, 1985
    Date of Patent: June 16, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Ryohei Satoh, Muneo Oshima, Minoru Tanaka, Suguru Sakaguchi, Akira Murata, Kazuo Hirota