Patents by Inventor Suguru Tsuchiya

Suguru Tsuchiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7199892
    Abstract: When a multicast instruction is input, a facsimile apparatus transmits an input plurality of sub-addresses together with image data to a repeater in a single communication transaction. Thus, effective communication can be performed.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: April 3, 2007
    Assignee: Panasonic Communications Co., Ltd.
    Inventor: Suguru Tsuchiya
  • Patent number: 6583889
    Abstract: At the time of rewriting a program provided in a facsimile apparatus using a memory card, a mode is changed by determining the content of the memory card and the presence and absence of a predetermined operation. Then, at the time of rewriting the program, the program is rewritten to a program stored in the memory card regardless of old and new versions, while the content of the memory card is erased as required.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: June 24, 2003
    Assignee: Panasonic Communications Co., Ltd.
    Inventors: Izumi Koyanagi, Nobuhiro Moteki, Suguru Tsuchiya, Shinichi Mitaku, Takafumi Higuchi
  • Publication number: 20020054367
    Abstract: When a multicast instruction is input, a facsimile apparatus transmits an input plurality of sub-addresses together with image data to a repeater in a single communication transaction. Thus, effective communication can be performed.
    Type: Application
    Filed: July 16, 2001
    Publication date: May 9, 2002
    Applicant: MATSUSHITA GRAPHIC COMMUNICATION SYSTEMS, Inc.
    Inventor: Suguru Tsuchiya
  • Patent number: 5684602
    Abstract: A facsimile apparatus comprises a receiving buffer for receiving video data, a scanner for reading an image, a VRAM for storing a coded data, a single coding/decoding (C/D) IC for MR-coding, MR-to-MMR coding, decoding, and error-checking, and a page printer, and a control circuit, when an event requiring more than two operations of the C/D IC at the same time, the control circuit permits only one operation and force the other operations to wait in some condition. In another condition, the control circuit permits one of the other operation and force the other operations to wait. For example, when the scanner reads an image to produce read data and the C/D IC codes the read data to store the read data in the VRAM and there is a call, the control means connects the line but keeps the coding if the receiving buffer has a space. In the presence of the space the control circuit interrupt the coding and starts the decoding.
    Type: Grant
    Filed: June 29, 1994
    Date of Patent: November 4, 1997
    Assignee: Matsushita Graphic Communication Systems, Inc.
    Inventors: Suguru Tsuchiya, Mitsutoshi Tsukamoto, Tadanori Ipponyari, Takafumi Higuchi, Katsuya Okamoto, Masahiro Hayashi