Patents by Inventor Suhas Mysore Satheesh

Suhas Mysore Satheesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9255967
    Abstract: A system and method are provided for measuring an integrated circuit age. A first clock generator is provided for generating a first clock signal and a second clock generator is provided for generating a second clock signal. Further, a phase detector in communication with the first clock generator and the second clock generator is provided for receiving the first clock signal from the first clock generator and the second clock signal from the second clock generator, and outputting a phase difference signal that is capable of being used as a measure of an integrated circuit age. Still yet, a circuit in communication with the phase detector and the first clock generator is provided for receiving the first clock signal from the first clock generator and the phase difference signal from the phase detector and for synchronizing the phase difference signal from the phase detector with the first clock signal from the first clock generator.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: February 9, 2016
    Assignee: NVIDIA Corporation
    Inventors: Rubil Ahmadi, Varghese George, Suhas Mysore Satheesh
  • Publication number: 20140306687
    Abstract: A system and method are provided for measuring an integrated circuit age. A first clock generator is provided for generating a first dock signal. Additionally, a second clock generator is provided for generating a second clock signal. Further, a phase detector is provided that is in communication with the first dock generator and the second dock generator. The phase detector is operable for receiving the first clock signal from the first clock generator and the second clock signal from the second dock generator, and outputting a phase difference signal. Still yet, a circuit is provided that is in communication with the phase detector and the first clock generator. The circuit is operable for receiving the first clock signal from the first clock generator and the phase difference signal from the phase detector. The circuit is further operable for synchronizing the phase difference signal from the phase detector with the first dock signal from the first clock generator.
    Type: Application
    Filed: April 11, 2013
    Publication date: October 16, 2014
    Applicant: NVIDIA Corporation
    Inventors: Rubil Ahmadi, Varghese George, Suhas Mysore Satheesh