Abstract: Driver circuits to invert an input signal and to generate an output signal based on the inverted input signal are presented. The voltage level of the logical high value of the output signal is adjustable. The driver circuit has a high side switching element coupled between a supply terminal and the output terminal of the driver circuit. The driver circuit has a low side switching element coupled between the output terminal of the driver circuit and a reference potential. The driver circuit has a regulation transistor, wherein a controlled section of the regulation transistor is coupled in series with the high side switching element and the low side switching element between the supply terminal and the reference potential. The driver circuit has a feedback circuit to regulate the output voltage by generating a regulation voltage at a control terminal of the regulation transistor.

Abstract: An electrical overstress (EOS) protection circuit that at least partially neutralizes or compensates for undershoot and overshoot in first and second signals that are communicated using differential signaling, such as with USB communications. For an undershoot, the EOS protection circuit injects charge into pads that receive the first and second signals. For an overshoot, the EOS protection circuit drains charge from the pad that receives the second signal and injects charge into the pad that receives the first signal.

Abstract: An electrical overstress (EOS) protection circuit that at least partially neutralizes or compensates for undershoot and overshoot in first and second signals that are communicated using differential signaling, such as with USB communications. For an undershoot, the EOS protection circuit injects charge into pads that receive the first and second signals. For an overshoot, the EOS protection circuit drains charge from the pad that receives the second signal and injects charge into the pad that receives the first signal.

Abstract: An electrical overstress (EOS) protection circuit that at least partially neutralizes or compensates for undershoot and overshoot in first and second signals that are communicated using differential signaling, such as with USB communications. For an undershoot, the EOS protection circuit injects charge into pads that receive the first and second signals. For an overshoot, the EOS protection circuit drains charge from the pad that receives the second signal and injects charge into the pad that receives the first signal.

Abstract: An electrical overstress (EOS) protection circuit that at least partially neutralizes or compensates for undershoot and overshoot in first and second signals that are communicated using differential signaling, such as with USB communications. For an undershoot, the EOS protection circuit injects charge into pads that receive the first and second signals. For an overshoot, the EOS protection circuit drains charge from the pad that receives the second signal and injects charge into the pad that receives the first signal.

Abstract: The present invention provides a method and system for open loop compensation of delay variations in a delay line. The method includes sensing the Process, Voltage, Temperature (PVT) variations in the delay line using a sensing circuit. A first and second sensitive current are generated based on the PVT variations. The first and second sensitive currents are mirrored currents from the sensing circuit. Then, a first compensation current is generated based on the first sensitive current and a first summing current. The first summing current is a reference current independent of the PVT variations. Further, the first compensation current is mirrored as a second summing current and a second compensation current is generated from the second sensitive current and the second summing current. The second compensation current compensates the delay variations and has a sensitivity based on the sensitivities of the first and second sensitive currents.

Abstract: The present invention provides a method and system for open loop compensation of delay variations in a delay line. The method includes sensing the Process, Voltage, Temperature (PVT) variations in the delay line using a sensing circuit. A first and second sensitive current are generated based on the PVT variations. The first and second sensitive currents are mirrored currents from the sensing circuit. Then, a first compensation current is generated based on the first sensitive current and a first summing current. The first summing current is a reference current independent of the PVT variations. Further, the first compensation current is mirrored as a second summing current and a second compensation current is generated from the second sensitive current and the second summing current. The second compensation current compensates the delay variations and has a sensitivity based on the sensitivities of the first and second sensitive currents.