Abstract: The present invention provides a method for synthesizing etelcalcetide or salts thereof, comprising the steps of: (a) synthesizing the D-amino acids in the formula (I) sequentially by Fmoc solid-phase synthesis, using a solid support as a starting material in solid phase peptide synthesis and sequentially synthesizing a D-form amino acid of formula (I) by Fmoc chemistry; deprotecting Fmoc group and acetylating the amino group to obtain a sequence A comprising protecting groups (PG) in the side chain of D-Cys and D-Arg; (b) removing the protecting group in the side-chain of D-Cys of the sequence A to form a sequence B; (c) disulfide formation at D-Cys of the sequence B by (PG)-L-Cys-OH to obtain a sequence C; (d) using a cleavage solution to remove the protecting groups of the sequence C to give etelcalcetide as formula (I). The present invention can shorten the steps and time for preparing Etelcalcetide.

Abstract: The present invention provides a method for synthesizing etelcalcetide or salts thereof, comprising the steps of: (a) synthesizing the D-amino acids in the formula (I) sequentially by Fmoc solid-phase synthesis, using a solid support as a starting material in solid phase peptide synthesis and sequentially synthesizing a D-form amino acid of formula (I) by Fmoc chemistry; deprotecting Fmoc group and acetylating the amino group to obtain a sequence A comprising protecting groups (PG) in the side chain of D-Cys and D-Arg; (b) removing the protecting group in the side-chain of D-Cys of the sequence A to form a sequence B; (c) disulfide formation at D-Cys of the sequence B by (PG)-L-Cys-OH to obtain a sequence C; (d) using a cleavage solution to remove the protecting groups of the sequence C to give etelcalcetide as formula (I). The present invention can shorten the steps and time for preparing Etelcalcetide.

Abstract: A frequency synthesizing device includes a voltage-controlled oscillator receiving an adjusting signal and generating an output signal according to the adjusting signal. A feedback frequency divider having a plurality of divisor values receives the output signal and generates a feedback signal after performing frequency dividing. An automatic frequency calibration circuit of the frequency synthesizing device includes a first frequency divider receiving a reference frequency, and a second frequency divider receiving the feedback signal. A comparator of the automatic frequency calibration circuit receives and compares outputs from the first frequency divider and the second frequency divider in a predetermined period to generate a comparing result. A state machine outputs the adjusting signal according to the comparing result in a calibration mode.

Abstract: A frequency synthesizing device includes a voltage-controlled oscillator receiving an adjusting signal and generating an output signal according to the adjusting signal. A feedback frequency divider having a plurality of divisor values receives the output signal and generates a feedback signal after performing frequency dividing. An automatic frequency calibration circuit of the frequency synthesizing device includes a first frequency divider receiving a reference frequency, and a second frequency divider receiving the feedback signal. A comparator of the automatic frequency calibration circuit receives and compares outputs from the first frequency divider and the second frequency divider in a predetermined period to generate a comparing result. A state machine outputs the adjusting signal according to the comparing result in a calibration mode.

Abstract: A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability.

Abstract: A semiconductor structure includes a semiconductor chip having at least an electrode pad, a first metal layer formed on the electrode pad, a second metal layer completely formed on and in contact with the first metal layer, and a conductive pillar disposed on the second metal layer, where a material of the first metal layer is different from a material of the second metal layer, the first metal layer has a first distribution-projected area larger than a second distribution projected-area of the conductive pillar, and the second metal layer has a third distribution-projected area that is the same as the second distribution-projected area of the conductive pillar.

Abstract: A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer.

Abstract: A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability.

Abstract: A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer.

Abstract: A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer.

Abstract: A cleaning apparatus is disclosed to include a housing, a conical receptacle fixedly provided inside the housing for holding an umbrella in an inverted and partially opened condition, a vacuum pump fixedly mounted inside the housing and connected to the conical receptacle for producing a negative pressure to suck in dust and water from the inserted umbrella in the conical receptacle, and a hot air blower installed in the housing for flowing hot current of air into the inside of the conical receptacle to dry the inserted umbrella.