Abstract: The present invention provides methods and systems for providing efficient use of available CPU cycles that may be achieved by reducing the length of the echo canceller filter. An echo canceller's adaptive algorithm may be implemented to reach a lower mean squared error due to the increased training time allowed by cycle reduction. Total power consumption of a processor may be reduced by reducing the number of multiplications (and/or other operations) that may be performed by an echo canceller filter for each time iteration. This may be achieved by not performing multiplications on taps that are not being used. For higher rates, a shorter echo canceller filter may be implemented by transmitting less energy in low frequencies. As a result, the temporal length of the echo channel may be shortened thereby reducing the total number of taps needed to model the channel. The present invention may further enhance performance by reducing CPU cycles and allowing for more echo canceller training time.

Abstract: The present invention is directed to methods and systems for providing an accurate estimate of the channel capacity that may be performed for each symbol rate tested during line probe. In addition, an optimal symbol rate under a set of conditions may be determined using the capacities for each tested symbol rate. In the G.SHDSL (or other) standard, provisions may be made for rate negotiation to take place between two communicating modems after a line probe session. The present invention provides an approach to rate negotiation that implements an approximation of channel capacity using a geometric mean calculation. The capacity for a plurality of M frequency sub-bands may be computed to find an estimate of channel capacity for a rate of interest. The sub-bands may be any segment of a total N frequency bands found with a discrete Fourier transform (DFT) or other method of spectrum estimation.

Abstract: The present invention provides methods and systems for improving the performance of a pair of non discrete multi-tone based digital subscriber line modems by choosing transmitted power spectral densities according to line conditions. The G.SHDSL and HDSL2 standards, for example, may specify the transmitted power to be less than a certain value at any given frequency. The present invention provides a method and system for shaping power spectral density based on line conditions where first line condition data associated with a first modem is determined; second line condition data associated with a second modem is determined; the first and second line condition data are exchanged, and a transmit spectrum is shaped in response thereto.

Abstract: The present invention is directed to methods and systems for determining maximum power backoff for modems operating according to G.SHDSL and other standards using frequency domain geometric signal to noise ratio (SNR). In one example, a G.SHDSL standard may specify a minimum power back off (PBO) that may be required for modem implementation. Although the standard specifies the minimum back off, it is desirable to be able to increase the PBO beyond this level. The reasons for this may include reduced power consumption and reduced crosstalk generated by a modem. The present invention discloses a method and system for determining an absolute maximum power PBO that may be tolerated and still meet bit error rate (BER) and/or other requirements. The present invention implements a geometric mean to compute SNR in a frequency domain over a pass-band of a transmit spectrum.

Abstract: The present invention, generally speaking, provides a digitally-tunable, echo-cancelling analog front end (AFE) for wireline digital communications. The analog front end is especially useful in a High-bit-rate Digital Subscriber Line (HDSL) or HDSL2 environment. An analog echo simulation path is provided capable of simulating echo from a wide variety of echo paths. Digitally controlled attenuators are provided in the transmission path and in the analog echo simulation path. Also provided is a digital-tunable equalizer stage. The equalizer stage is tuned to match the characteristics of the receive path. The same arrangement may be adapted for various DSL technologies, i.e., xDSL. There results an analog front end that is well-adapted to high-speed wireline communications.