Patents by Inventor Sujan Kundapur Manohar
Sujan Kundapur Manohar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11575372Abstract: A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.Type: GrantFiled: May 18, 2020Date of Patent: February 7, 2023Assignee: Texas Instruments IncorporatedInventors: Sujan Kundapur Manohar, Michael James Mills, Justin Patrick Vogt
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Publication number: 20220415768Abstract: A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement.Type: ApplicationFiled: August 30, 2022Publication date: December 29, 2022Inventors: Jeffrey MORRONI, Rajeev Dinkar JOSHI, Sreenivasan K. KODURI, Sujan Kundapur MANOHAR, Yogesh K. RAMADASS, Anindya PODDAR
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Patent number: 11430722Abstract: A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement.Type: GrantFiled: April 11, 2018Date of Patent: August 30, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey Morroni, Rajeev Dinkar Joshi, Sreenivasan K. Koduri, Sujan Kundapur Manohar, Yogesh K. Ramadass, Anindya Poddar
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Patent number: 10979037Abstract: In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors.Type: GrantFiled: October 22, 2018Date of Patent: April 13, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sujan Kundapur Manohar, Roland Karl Son, Juergen Luebbe, Eddie W. Yu
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Patent number: 10782727Abstract: Integrated circuits having self-calibrating oscillators, and methods of operating the same are disclosed. A disclosed example integrated circuit includes a clock generator, a comparator having a first input connected to an output of the clock generator and a second input connected to a reference voltage, a calibration done detector having an input connected to an output of the comparator and an output communicatively coupled to a calibration code register.Type: GrantFiled: November 19, 2018Date of Patent: September 22, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Angelo William Pereira, Pinar Korkmaz, Sujan Kundapur Manohar
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Publication number: 20200280309Abstract: A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.Type: ApplicationFiled: May 18, 2020Publication date: September 3, 2020Inventors: Sujan Kundapur Manohar, Michael James Mills, Justin Patrick Vogt
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Patent number: 10734313Abstract: A semiconductor package includes a leadframe and a semiconductor die attached to the leadframe by way of solder posts. In a stacked arrangement, the package also includes a passive component disposed between the leadframe and the semiconductor die and electrically connected to the semiconductor die through the leadframe.Type: GrantFiled: April 11, 2018Date of Patent: August 4, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey Morroni, Rajeev Dinkar Joshi, Sreenivasan K. Koduri, Sujan Kundapur Manohar, Yogesh K. Ramadass, Anindya Poddar
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Patent number: 10673423Abstract: In described examples, in response to a voltage at an external power terminal falling below a safe limit: a charge pump is operated at a first frequency to produce a voltage at a charge pump node; and a first controlled current is coupled from the charge pump node to a control terminal of a power switch transistor. The power switch transistor has a conduction path coupled between the external power terminal and an internal power terminal at which an internal power source is connected. In response to the voltage at the external power terminal reaching a selected level: the charge pump is operated at a second frequency, lower than the first frequency; and a second controlled current, lower than the first controlled current, is coupled from the charge pump node to the control terminal of the power switch transistor.Type: GrantFiled: August 11, 2016Date of Patent: June 2, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hassan Pooya Forghani-Zadeh, Sujan Kundapur Manohar, Ariel Dario Moctezuma
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Publication number: 20200159278Abstract: Integrated circuits having self-calibrating oscillators, and methods of operating the same are disclosed. A disclosed example integrated circuit includes a clock generator, a comparator having a first input connected to an output of the clock generator and a second input connected to a reference voltage, a calibration done detector having an input connected to an output of the comparator and an output communicatively coupled to a calibration code register.Type: ApplicationFiled: November 19, 2018Publication date: May 21, 2020Inventors: Angelo William Pereira, Pinar Korkmaz, Sujan Kundapur Manohar
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Patent number: 10659033Abstract: A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.Type: GrantFiled: November 3, 2017Date of Patent: May 19, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sujan Kundapur Manohar, Michael James Mills, Justin Patrick Vogt
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Patent number: 10613564Abstract: A voltage regulator (such as a low drop-out regulator) includes a pass transistor coupled to an input voltage node and an output voltage node. The voltage regulator also includes a drive transistor coupled to a control input of the pass transistor and a first resistor coupled between a source and a back gate of the drive transistor. The voltage regulator also includes a complementary to absolute temperature (CTAT) current generator circuit coupled to the resistor and configured to generate a CTAT current to bias the first resistor.Type: GrantFiled: January 14, 2019Date of Patent: April 7, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sujan Kundapur Manohar, Angelo William Pereira, Ashish Khandelwal
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Patent number: 10523114Abstract: Described herein is a technology for implementing a decoupling circuit (104) to increase reliability of a DC-DC power converter (100). To absorb an overshoot transient voltage, the decoupling circuit includes a first capacitor (214) and a second capacitor (216) that charge energy during a short burst of upward electrical energy. During an undershoot transient voltage, however, the first capacitor and second capacitor discharge energy to a transistor (108). In certain embodiment, such as the transistor that requires higher voltage switching, the decoupling circuit is connected in series with another decoupling circuit.Type: GrantFiled: November 29, 2018Date of Patent: December 31, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sujan Kundapur Manohar, Yogesh K. Ramadass
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Publication number: 20190146536Abstract: A voltage regulator (such as a low drop-out regulator) includes a pass transistor coupled to an input voltage node and an output voltage node. The voltage regulator also includes a drive transistor coupled to a control input of the pass transistor and a first resistor coupled between a source and a back gate of the drive transistor. The voltage regulator also includes a complementary to absolute temperature (CTAT) current generator circuit coupled to the resistor and configured to generate a CTAT current to bias the first resistor.Type: ApplicationFiled: January 14, 2019Publication date: May 16, 2019Inventors: Sujan Kundapur Manohar, Angelo William Pereira, Ashish Khandelwal
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Publication number: 20190140631Abstract: A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.Type: ApplicationFiled: November 3, 2017Publication date: May 9, 2019Inventors: SUJAN KUNDAPUR MANOHAR, MICHAEL JAMES MILLS, JUSTIN PATRICK VOGT
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Publication number: 20190058463Abstract: In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors.Type: ApplicationFiled: October 22, 2018Publication date: February 21, 2019Inventors: Sujan Kundapur Manohar, Roland Karl Son, Juergen Luebbe, Eddie W. Yu
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Patent number: 10180694Abstract: A voltage regulator (e.g., a low drop-out regulator) includes a pass transistor coupled to an input voltage node and an output voltage node. The voltage regulator also includes a drive transistor coupled to a control input of the pass transistor and a first resistor coupled between a source and a back gate of the drive transistor. The voltage regulator also includes a complementary to absolute temperature (CTAT) current generator circuit coupled to the resistor and configured to generate a CTAT current to bias the first resistor.Type: GrantFiled: July 20, 2017Date of Patent: January 15, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sujan Kundapur Manohar, Angelo William Pereira, Ashish Khandelwal
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Patent number: 10116291Abstract: In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors.Type: GrantFiled: August 9, 2016Date of Patent: October 30, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sujan Kundapur Manohar, Roland Karl Son, Juergen Luebbe, Eddie W. Yu
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Publication number: 20180301403Abstract: A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement.Type: ApplicationFiled: April 11, 2018Publication date: October 18, 2018Inventors: Jeffrey MORRONI, Rajeev Dinkar JOSHI, Sreenivasan K. KODURI, Sujan Kundapur MANOHAR, Yogesh K. RAMADASS, Anindya PODDAR
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Publication number: 20180301402Abstract: A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in which at least a portion of the passive component is disposed in a stacked arrangement.Type: ApplicationFiled: April 11, 2018Publication date: October 18, 2018Inventors: Jeffrey MORRONI, Rajeev Dinkar JOSHI, Sreenivasan K. KODURI, Sujan Kundapur MANOHAR, Yogesh K. RAMADASS, Anindya PODDAR
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Publication number: 20180301404Abstract: A semiconductor package includes a leadframe and a semiconductor die attached to the leadframe by way of solder posts. In a stacked arrangement, the package also includes a passive component disposed between the leadframe and the semiconductor die and electrically connected to the semiconductor die through the leadframe.Type: ApplicationFiled: April 11, 2018Publication date: October 18, 2018Inventors: Jeffrey MORRONI, Rajeev Dinkar JOSHI, Sreenivasan K. KODURI, Sujan Kundapur MANOHAR, Yogesh K. RAMADASS, Anindya PODDAR