Patents by Inventor Sujan Manobar

Sujan Manobar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus of a level shifter circuit having a structure to reduce fall and rise path delay
    Patent number: 7511552
    Abstract: A method, apparatus and/or system of a level shifter circuit having a structure to reduce fall and rise path delay is disclosed. In one embodiment, a level shifter circuit comprise a first set of sequentially coupled pull-up and pull-down sub-circuits cross coupled to a second set of sequentially pull-up and pull-down sub-circuits to generate a positive feedback loop; an output node coupled to a shared node between the first pull-up and pull-down sub-circuits through an output inverter; a pull-up NMOS transistor with a gate contact coupled to the input of the second set, a source contact coupled to an input of the output inverter and a drain contact coupled to the output voltage of the level shifter circuit; and a pull-down NMOS transistor with a gate contact coupled to the input of the second set, a drain contact coupled to an output of the output inverter and a source contact coupled to a ground.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: March 31, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Shahid Ali, Satheesh Balasubramanian, Sujan Manobar
  • Method and apparatus of a level shifter circuit having a structure to reduce fall and rise path delay
    Publication number: 20070290735
    Abstract: A method, apparatus and/or system of a level shifter circuit having a structure to reduce fall and rise path delay is disclosed. In one embodiment, a level shifter circuit comprise a first set of sequentially coupled pull-up and pull-down sub-circuits cross coupled to a second set of sequentially pull-up and pull-down sub-circuits to generate a positive feedback loop; an output node coupled to a shared node between the first pull-up and pull-down sub-circuits through an output inverter; a pull-up NMOS transistor with a gate contact coupled to the input of the second set, a source contact coupled to an input of the output inverter and a drain contact coupled to the output voltage of the level shifter circuit; and a pull-down NMOS transistor with a gate contact coupled to the input of the second set, a drain contact coupled to an output of the output inverter and a source contact coupled to a ground.
    Type: Application
    Filed: June 15, 2006
    Publication date: December 20, 2007
    Inventors: Shahid Ali, Satheesh Balasubramanian, Sujan Manobar