Abstract: Aspects of the present disclosure provide for a method. In some examples, the method includes receiving a synchronization signal, dividing the synchronization signal to form a first divided signal and a second divided signal, generating a first ramp signal and a second ramp signal, setting a latch output to a logical high value when the first divided signal has a logical high value or a value of the first ramp signal exceeds a value of a reference signal, setting the latch output to a logical low value when the second divided signal has a logical high value or a value of the second ramp signal exceeds the value of the reference signal, generating a synchronization clock according to the latch output and an inverse of the latch output, and outputting the latch output or the synchronization clock as a clock signal based on a value of a synchronization active signal.

Abstract: Aspects of the present disclosure provide for a method. In some examples, the method includes receiving a synchronization signal, dividing the synchronization signal to form a first divided signal and a second divided signal, generating a first ramp signal and a second ramp signal, setting a latch output to a logical high value when the first divided signal has a logical high value or a value of the first ramp signal exceeds a value of a reference signal, setting the latch output to a logical low value when the second divided signal has a logical high value or a value of the second ramp signal exceeds the value of the reference signal, generating a synchronization clock according to the latch output and an inverse of the latch output, and outputting the latch output or the synchronization clock as a clock signal based on a value of a synchronization active signal.

Abstract: Edge-sensitive Feedback-controlled pulse generator. A circuit includes a pulse generating circuit responsive to a desired transition in an input signal to initiate an output pulse. The circuit also includes a delay circuit responsive to the output pulse to generate a feedback signal. Further, the circuit includes a first latch that renders the pulse generating circuit unresponsive to any change in the input signal until the feedback signal has been generated, a switch responsive to the feedback signal to complete the output pulse, a second latch responsive to a change in the input signal after the feedback signal has been generated to render the pulse generating circuit responsive to a subsequent occurrence of the desired transition in the input signal to initiate the output pulse again, and a third latch responsive to the change in the input signal after the feedback signal has been generated.

Abstract: A method, system, and apparatus to a novel single supply level shifter circuit for multi-voltage designs, capable of up/down shifting are disclosed. In one embodiment, a system includes a first circuit, a second circuit, a voltage source with an output voltage equal to a voltage value of the second circuit, a level shifter circuit coupled with both an output of the first circuit and an output of the voltage source and wherein the level shifter circuit is used to convert a voltage value of a signal from the first circuit to the voltage value of the second circuit, and a capacitor loop circuit associated with the first circuit, the level shifter circuit and the voltage source and configured with a capacitor to charge from at least one of a first circuit output voltage.

Abstract: A method, system, and apparatus to a novel single supply level shifter circuit for multi-voltage designs, capable of up/down shifting are disclosed. In one embodiment, a system includes a first circuit, a second circuit, a voltage source with an output voltage equal to a voltage value of the second circuit, a level shifter circuit coupled with both an output of the first circuit and an output of the voltage source and wherein the level shifter circuit is used to convert a voltage value of a signal from the first circuit to the voltage value of the second circuit, and a capacitor loop circuit associated with the first circuit, the level shifter circuit and the voltage source and configured with a capacitor to charge from at least one of a first circuit output voltage.

Abstract: Equal delay flip-flop systems and complementary input complementary output equal delay flip-flop circuits are disclosed. In one embodiment, an equal delay flip-flop system includes a first delay flip-flop for processing a first input, including a first tri-state input driver for driving the first input, a first master latch for sampling and/or forwarding the first input, a first transmission gate for relaying the first input forwarded by the first master latch, and a first slave latch for storing and/or forwarding the first input. The equal delay flip-flop system further includes a second delay flip-flop for processing a second input, including a second tri-state input driver for driving the second input, a second master latch for sampling and/or forwarding the second input, a second transmission gate for relaying the second input forwarded by the second master latch, and a second slave latch for storing and/or forwarding the second input.

Abstract: A method and/or a system of control signal synchronization of a scannable storage circuit is disclosed. In one embodiment, a system includes a first circuit to operate based on a first voltage of a first power supply, a second circuit to operate based on a second voltage of a second power supply, a level shifter circuit between the first circuit and the second circuit to translate between the first voltage of the first power supply and the second voltage of the second power supply, and a n-channel metal-oxide semiconductor field-effect transistor (nMOSFET) having a gate input of the second voltage and serially coupled in a fall path of the level shifter circuit to increase a rate of a capacitive discharge such that the rate of a capacitive discharge charge is substantially equal to a rate of a capacitive charge (e.g., the fall delay may also increase a bit because of an extra transistor).

Abstract: A flip-flop is configured for low standby/leakage power for power-conservation, especially in battery operated portable devices using flip-flops. The flip-flop uses a clock and may be a D flip-flop, including a master latch with first and second inverters and a slave latch. The inverters in the master-latch are configured to be selectively gated. The gating is preferably done by first and second transistors receiving the clock signal and connected between a voltage source and the ground. The gating cuts off power supply to the inverters when the clock is low and reduces leakage power. The slave latch includes a primary inverter and a feedback inverter. Expediently, a transmission gate between the master-latch and the slave-latch is eliminated. The primary inverter in the slave-latch is not gated to prevent the input of the feedback inverter from going into a “floating” state.

Abstract: A method and/or a system of control signal synchronization of a scannable storage circuit is disclosed. In one embodiment, a system includes a first circuit to operate based on a first voltage of a first power supply, a second circuit to operate based on a second voltage of a second power supply, a level shifter circuit between the first circuit and the second circuit to translate between the first voltage of the first power supply and the second voltage of the second power supply, and a n-channel metal-oxide semiconductor field-effect transistor (nMOSFET) having a gate input of the second voltage and serially coupled in a fall path of the level shifter circuit to increase a rate of a capacitive discharge such that the rate of a capacitive discharge charge is substantially equal to a rate of a capacitive charge (e.g., the fall delay may also increase a bit because of an extra transistor).