Abstract: A clock generator outputs a processor clock that serves as an operation reference for a processor for use in a content protection system. The clock generator includes a direct digital synthesis and a random number generator. The direct digital synthesizer includes a phase accumulator and outputs the processor clock. The phase accumulator accumulates a setup value in synchronization with a reference clock. The random number generator generates random numbers. The setup value changes based on the random numbers.

Abstract: A transmission device includes a converter and a transmitter. The converter converts a plurality of link symbols in DisplayPort (DP) into a data block in Gen 2 in Universal Serial Bus (USB). The transmitter transmits the data block.

Abstract: A DisplayPort (DP) High-bandwidth Digital Content Protection (HDCP) version converter that converts an HDCP content protection version from input to output includes a receiver and a transmitter. The receiver receives a serial bit stream transmitted from an upstream device, and decrypts link symbols of the received serial bit stream by use of a decryption unit. The transmitter encrypts, by use of an encryption unit, the link symbols decrypted by the receiver, and converts the encrypted link symbols into a serial bit stream and transmits the serial bit stream to a downstream device. The receiver and the transmitter have the same link configuration.

Abstract: A transmission device includes a converter and a transmitter. The converter converts a plurality of link symbols in DisplayPort (DP) into a data block in Gen 2 in Universal Serial Bus (USB). The transmitter transmits the data block.

Abstract: A clock generator outputs a processor clock that serves as an operation reference for a processor for use in a content protection system. The clock generator includes a direct digital synthesis and a random number generator. The direct digital synthesizer includes a phase accumulator and outputs the processor clock. The phase accumulator accumulates a setup value in synchronization with a reference clock. The random number generator generates random numbers. The setup value changes based on the random numbers.

Abstract: A DisplayPort (DP) High-bandwidth Digital Content Protection (HDCP) version converter that converts an HDCP content protection version from input to output includes a receiver and a transmitter. The receiver receives a serial bit stream transmitted from an upstream device, and decrypts link symbols of the received serial bit stream by use of a decryption unit. The transmitter encrypts, by use of an encryption unit, the link symbols decrypted by the receiver, and converts the encrypted link symbols into a serial bit stream and transmits the serial bit stream to a downstream device. The receiver and the transmitter have the same link configuration.

Abstract: A method of automatic gain control in both analog and digital domain is performed by receiving an incoming analog signal, determining an overall gain factor, determining a coarse analog gain control value and a fine digital gain control value, each of which, when taken together substantially equals the already determined overall gain factor, modifying the incoming analog signal using the coarse analog gain control value to form a coarsely adjusted digital signal, digitizing the coarsely adjusted digital signal, and using the fine digital gain control value to process the coarsely adjusted digital signal to form an outgoing digital signal, wherein the outgoing digital signal has been modified in both the analog domain and subsequently in the digital domain to achieve an appropriate signal to noise ratio.

Abstract: A method of automatic gain control in both analog and digital domain is performed by receiving an incoming analog signal, determining an overall gain factor, determining a coarse analog gain control value and a fine digital gain control value, each of which, when taken together substantially equals the already determined overall gain factor, modifying the incoming analog signal using the coarse analog gain control value to form a coarsely adjusted digital signal, digitizing the coarsely adjusted digital signal, and using the fine digital gain control value to process the coarsely adjusted digital signal to form an outgoing digital signal, wherein the outgoing digital signal has been modified in both the analog domain and subsequently in the digital domain to achieve an appropriate signal to noise ratio.