Patents by Inventor Sujat Jamil

Sujat Jamil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10230542
    Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: March 12, 2019
    Assignee: Marvell World Trade Ltd.
    Inventors: Eitan Joshua, Shaul Chapman, Erez Amit, Noam Mizrahi, Moshe Raz, Husam Khshaiboun, Amit Shmilovich, Sujat Jamil, Frank O'Bleness
  • Patent number: 10083126
    Abstract: An apparatus and method are provided for avoiding conflicting entries in a storage structure. The apparatus comprises a storage structure having a plurality of entries for storing data, and allocation circuitry, responsive to a trigger event for allocating new data into the storage structure, to determine a victim entry into which the new data is to be stored, and to allocate the new data into the victim entry upon determining that the new data is available. Conflict detection circuitry is used to detect when the new data will conflict with data stored in one or more entries of the storage structure, and to cause the data in said one or more entries to be invalidated. The conflict detection circuitry is arranged to perform, prior to a portion of the new data required for conflict detection being available, at least one initial stage detection operation to determine, based on an available portion of the new data, candidate entries whose data may conflict with the new data.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: September 25, 2018
    Assignee: ARM Limited
    Inventors: Richard F Bryant, Max John Batley, Lilian Atieno Hutchins, Sujat Jamil
  • Publication number: 20180157601
    Abstract: An apparatus and method are provided for avoiding conflicting entries in a storage structure. The apparatus comprises a storage structure having a plurality of entries for storing data, and allocation circuitry, responsive to a trigger event for allocating new data into the storage structure, to determine a victim entry into which the new data is to be stored, and to allocate the new data into the victim entry upon determining that the new data is available. Conflict detection circuitry is used to detect when the new data will conflict with data stored in one or more entries of the storage structure, and to cause the data in said one or more entries to be invalidated. The conflict detection circuitry is arranged to perform, prior to a portion of the new data required for conflict detection being available, at least one initial stage detection operation to determine, based on an available portion of the new data, candidate entries whose data may conflict with the new data.
    Type: Application
    Filed: December 6, 2016
    Publication date: June 7, 2018
    Inventors: Richard F. BRYANT, Max John BATLEY, Lilian Atieno HUTCHINS, Sujat JAMIL
  • Patent number: 9934152
    Abstract: Systems and techniques relating to hardware alias detection and management in caches are described. A cache controller can receive a cache request that specifies a virtual address, which includes a virtual page number (VPN) and a page offset; access, concurrently, one or more primary tags in a slot of the cache corresponding to a primary cache index that is based on a portion of the page offset and a portion of the VPN and one or more secondary tags in one or more slots corresponding to one or more secondary cache indices that are based on the portion of the page offset and one or more variations of the portion of the VPN; and determine whether there are any primary or secondary matching ways. The controller can write store data to a primary matching way if it exists and perform an alias management operation if any secondary matching ways exist.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: April 3, 2018
    Assignee: Marvell International Ltd.
    Inventors: Richard Bryant, R. Frank O'Bleness, Sujat Jamil, Kim Schuttenberg
  • Patent number: 9892051
    Abstract: A method can include executing a store instruction that instructs storing of data at an address and, in response to the store instruction, inserting a preloading instruction after the store instruction but before a dependent load instruction to the address. Executing the store instruction can include invalidating a data entry of a cache array at an address of the cache array corresponding to the address and writing the data to a backing memory at an address of the backing memory corresponding to the address. The preloading instruction can cause filling the data entry of the cache array, at the address of the cache array corresponding to the address, with the data from the backing memory at the address of the backing memory corresponding to the address and validating the data entry of the cache array.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: February 13, 2018
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Sujat Jamil, R. Frank O'Bleness, Russell J. Robideau, Tom Hameenanttila, Joseph Delgross, David E. Miner
  • Patent number: 9842051
    Abstract: A circuit includes a Virtually Indexed Physically Tagged (VIPT) cache and a cache coherency circuit. The VIPT cache includes a plurality of sets and performs a memory operation by selecting, using a Virtual Set Address (VSA), a first tag of a first set. The cache coherency circuit is to detect cache aliasing during memory operations of the VIPT cache when a second tag maps a physical address to a second set of the VIPT cache, the second set being different than the first set. A method of managing a VIPT cache includes performing, by the VIPT cache, a memory operation and determining, using a cache coherency protocol, that cache aliasing has occurred during the memory operation.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: December 12, 2017
    Assignee: Marvell International Ltd.
    Inventors: Kim Schuttenberg, Richard Bryant, Sujat Jamil, R. Frank O'Bleness
  • Publication number: 20170180156
    Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 22, 2017
    Inventors: Eitan Joshua, Shaul Chapman, Erez Amit, Noam Mizrahi, Moshe Raz, Husam Khshaiboun, Amit Shmilovich, Sujat Jamil, Frank O'Bleness
  • Patent number: 9606800
    Abstract: A microprocessor includes a front end module and a schedule queue module. The front end module is configured to retrieve first instructions, corresponding to a first thread, from an instruction cache, and retrieve second instructions, corresponding to a second thread, from the instruction cache. The front end module is also configured to decode the first instructions into first decoded instructions, and decode the second instructions into second decoded instructions. The schedule queue module is configured to selectively store the first decoded instructions and the second decoded instructions from the front end module and, for each stored decoded instruction, selectively issue the stored decoded instruction to an execution module. The schedule queue is further configured to reject storing an additional one of the first decoded instructions from the front end module in response to a count of the stored first decoded instructions in the schedule queue module exceeding a threshold.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 28, 2017
    Assignee: Marvell International Ltd.
    Inventors: Tom Hameenanttila, R. Frank O'Bleness, Sujat Jamil, Joseph Delgross
  • Patent number: 9454480
    Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: September 27, 2016
    Assignee: Marvell World Trade Ltd.
    Inventors: Eitan Joshua, Erez Amit, Shaul Chapman, Sujat Jamil, Frank O'Bleness
  • Patent number: 9442735
    Abstract: Apparatus having corresponding methods and computer-readable media comprise: a speculative store buffer memory; and a speculative store buffer controller comprising a store address comparator to compare an address of a received store instruction with addresses of store instructions allocated in the speculative store buffer memory, and a store age comparator to compare an age of the received store instruction with an age of a matching store instruction allocated in the speculative store buffer memory, wherein the speculative store buffer controller replaces the store instruction allocated in the speculative store buffer memory with the received store instruction responsive to the store instruction allocated in the speculative store buffer memory being younger than the received store instruction.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: September 13, 2016
    Assignee: Marvell International Ltd.
    Inventors: Sujat Jamil, R. Frank O'Bleness, Tom Hameenanttila, Joseph Delgross
  • Patent number: 9223709
    Abstract: A cache management unit manages allocation and configuration of a cache memory that is utilized by a multi-threaded processor. In some implementations, the cache management unit is configured to determine a number of active threads being executed by the multi-threaded processor, assign a separate cache unit to each active thread when the number of active threads is equal to a maximum number of active threads supported by the multi-threaded processor, and assign more than one cache unit to an active thread when the number of active threads is less than the maximum number of active threads.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: December 29, 2015
    Assignee: Marvell International Ltd.
    Inventors: R. Frank O'Bleness, Sujat Jamil, Tom Hameenanttila, Joseph Delgross
  • Patent number: 9116742
    Abstract: Systems, methods, and other embodiments associated with reducing interrupt latency are described. According to one embodiment, an apparatus includes a buffer storing instructions awaiting execution by an execution device. The apparatus also includes an interrupt logic that, in response to receiving an interrupt, classifies instructions as either safe or unsafe. An unsafe instruction will cause the instructions to execute in a manner inconsistent with an instruction set architecture. The interrupt logic also establishes an interrupt boundary between safe and unsafe instructions, and causes the interrupt to be processed at the interrupt boundary such that the interrupt is processed before processing of the unsafe instructions.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: August 25, 2015
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Kim Schuttenberg, Sujat Jamil, R. Frank O'Bleness
  • Patent number: 9086976
    Abstract: A system and method of tracking multiple non-identification tagged requests in a system with multiple responders are disclosed. In one embodiment, an electronic memory system comprises a memory configured to implement a plurality of response queues, wherein one response queue is associated with one responder from a plurality of responders, and wherein a responder is a device capable of resolving the memory request. A tracking module is configured to assign identification information to a memory request that is received and store the identification information in one or more queues of the plurality of response queues; and to transmit the memory request to each responder that is associated with the one or more queues. A response module is configured to associate the identification information in the one or more queues with a response upon receiving the response from the one or more responders.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: July 21, 2015
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: R. Frank O'Bleness, Sujat Jamil, David E. Miner, Tom Hameenanttila, Jeffrey Kehl, Richard Bryant, Kim Schuttenberg
  • Patent number: 9058272
    Abstract: An apparatus including a snoop filter decoupled from a cache and an associated method for snoop filtering are disclosed. The snoop filter is decoupled from the cache such that the cache changes states of lines in the cache from a first state that is a clean state, such as an exclusive (E) state, to a second state that is not a clean state, such as a modified (M) state, without the snoop filter's knowledge. The snoop filter buffers addresses of replaced lines that are unknown to be clean until a write-back associated with the replacement lines occurs, or until actual states of the replaced lines are determined by the snoop filter generating a snoop. A multi-level cache system in which a reallocation or replacement policy is biased to favor replacing certain lines such as inclusive lines, non-temporal lines or prefetched lines that have not been accessed, is also disclosed.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: June 16, 2015
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Frank O'Bleness, Sujat Jamil, David Miner, Joseph Delgross, Tom Hameenanttila, Jeffrey Kehl, Adi Habusha
  • Patent number: 9026769
    Abstract: A processor for processing loop instructions can include an instruction reorder structure and a loop processing controller. The instruction reorder structure is configured to store decoded instructions according to program order and issue the decoded instructions for execution out of program order. The loop processing controller is configured to detect a loop in the decoded instructions stored in the instruction reorder structure and cause the instruction reorder structure to reissue the decoded instructions that form the loop for re-execution.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: May 5, 2015
    Assignee: Marvell International Ltd.
    Inventors: Sujat Jamil, R. Frank O'Bleness, Joseph Delgross, Tom Hameenanttila
  • Patent number: 8990505
    Abstract: Devices, systems, methods, and other embodiments associated with a cache memory are described. In one embodiment, a cache tag array includes tag banks. The cache memory further includes a bank selector configured to receive an address and to apply a hash function that maps the address to one of the tag banks.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: March 24, 2015
    Assignee: Marvell International Ltd.
    Inventors: Sujat Jamil, R. Frank O'Bleness, David E. Miner, Joseph Delgross, Tom Hameenanttila
  • Patent number: 8943273
    Abstract: Aspects of the disclosure provide methods for cache efficiency. A method for cache efficiency can include storing data in a buffer entry in association with a cache array in response to a first store instruction that hits the cache array before the first store instruction is committed. Further, when a dependent load instruction is subsequent to the first store instruction, the method can include providing the data from the buffer entry in response to the first dependent load instruction. When a second store instruction overlaps an address of the first store instruction, the method can include coalescing data of the second store instruction in the buffer entry before the second store instruction is committed. When the second store instruction is followed by a second dependent load instruction, the method can include providing the coalesced data from the buffer entry in response to the second dependent load instruction.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: January 27, 2015
    Assignee: Marvell International Ltd.
    Inventors: Sujat Jamil, R. Frank O'Bleness, Russell Robideau, Tom Hameenanttila, Joseph Delgross, David Miner
  • Patent number: 8918625
    Abstract: A processor that executes instructions out of program order is described. In some implementations, a processor detects whether a second memory operation is dependent on a first memory operation prior to memory address calculation. If the processor detects that the second memory operation is not dependent on the first memory operation, the processor is configured to allow the second memory operation to be scheduled. If the processor detects that the second memory operation is dependent on the first memory operation, the processor is configured to prevent the second memory operation from being scheduled until the first memory operation has been scheduled to reduce the likelihood of having to reexecute the second memory operation.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: December 23, 2014
    Assignee: Marvell International Ltd.
    Inventors: R. Frank O'Bleness, Sujat Jamil, Tom Hameenanttila
  • Patent number: 8806181
    Abstract: According to some embodiments, an apparatus having corresponding methods includes a storage module configured to store data and instructions; a first processor pipeline configured to process the data and instructions when the first processor pipeline is selected; a second processor pipeline configured to process the data and instructions when the second processor pipeline is selected; and a selection module configured to select either the first processor pipeline or the second processor pipeline.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: August 12, 2014
    Assignee: Marvell International Ltd.
    Inventors: R. Frank O'Bleness, Sujat Jamil, Timothy S. Beatty, Franco Ricci, Tom Hameenanttila, Hong-Yi Chen
  • Publication number: 20140201445
    Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.
    Type: Application
    Filed: January 22, 2014
    Publication date: July 17, 2014
    Applicant: Marvell World Trade Ltd.
    Inventors: Eitan Joshua, Erez Amit, Shaul Chapman, Sujat Jamil, Frank O'Bleness