Abstract: A system and method for allowing jobs originating from different partitions to simultaneously utilize different hardware threads on a processor by concatenating partition identifiers with virtual page identifiers within a processor's translation lookaside buffer is presented. The device includes a translation lookaside buffer that translates concatenated virtual addresses to system-wide real addresses. The device generates concatenated virtual addresses using a partition identifier, which corresponds to a job's originating partition, and a virtual page identifier, which corresponds to the executing instruction, such as an instruction address or data address. In turn, each concatenated virtual address is different, which translates in the translation lookaside buffer to a unique system-wide real address. As such, jobs originating from different partitions are able to simultaneously execute on the device and, therefore, fully utilize each of the device's hardware threads.

Abstract: A method, system and computer program product for optimizing allocation of resources to partitions of a data processing system are disclosed. The method includes creating a first virtual central processing unit and a second virtual central processing unit, wherein at least one of the set of the first virtual processing unit and the second virtual processing spans across a first physical processing unit and a second physical processing unit. One or more resources from the first and second virtual central processing units are allocated to a first partition and a second partition. Whether one or more processes running on the first partition can utilize additional resources is determined. One or more resources from the first virtual central processing unit and resources from the second virtual central processing unit are reallocated to the first partition, wherein at least one of the resources was previously allocated to the second partition.

Abstract: A control mechanism that allows individual applications to turn hardware prefetch on or off is provided. By preliminary trial run one can determine precisely whether an application will benefit or suffer from hardware prefetch. The selective control of prefetching by individual applications is made possible by associating a status bit with individual processes in the machine status word of each processor. Using this prefetch bit, a process turns prefetching on or off to its own advantage in the processor core immediately after a context switch.

Abstract: A method, system and computer program product for optimizing allocation of resources to partitions of a data processing system are disclosed. The method includes creating a first virtual central processing unit and a second virtual central processing unit, wherein at least one of the set of the first virtual processing unit and the second virtual processing spans across a first physical processing unit and a second physical processing unit. One or more resources from the first and second virtual central processing units are allocated to a first partition and a second partition. Whether one or more processes running on the first partition can utilize additional resources is determined. One or more resources from the first virtual central processing unit and resources from the second virtual central processing unit are reallocated to the first partition, wherein at least one of the resources was previously allocated to the second partition.

Abstract: A method, system, and program for dynamic memory management of unallocated memory in a logical partitioned data processing system. A logical partitioned data processing system typically includes multiple memory units, processors, I/O adapters, and other resources enabled for allocation to multiple logical partitions. A partition manager operating within the data processing system manages allocation of the resources to each logical partition. In particular, the partition manager manages allocation of a first portion of the multiple memory units to at least one logical partition. In addition, the partition manager manages a memory pool of unallocated memory from among the multiple memory units. Responsive to receiving a request for a memory loan from one of the allocated logical partitions, a second selection of memory units from the memory pool is loaned to the requesting logical partition.

Abstract: The present invention provides a method, system, and apparatus for communicating to associative cache which data is least important to keep. The method, system, and apparatus determine which cache line has the least important data so that this less important data is replaced before more important data. In a preferred embodiment, the method begins by determining the weight of each cache line within the cache. Then the cache line or lines with the lowest weight is determined.

Abstract: Administration of locks for critical sections of computer programs in a computer that supports a multiplicity of logical partitions that include determining by a thread executing on a virtual processor executing in a time slice on a physical processor whether an expected lock time for a critical section of the thread exceeds a remaining entitlement of the virtual processor in the time slice and deferring acquisition of a lock if the expected lock time exceeds the remaining entitlement.

Abstract: A mechanism for generating pre-translated segments for use in virtual to real address translation is provided in which segments that are determined to meet a density threshold are promoted to a pre-translated segment class. The pages of these segments are moved to a contiguous portion of memory and the segment table entry corresponding to the segment is updated to indicate the segment to be a pre-translated segment and to include the base real address for the contiguous portion of memory. In one embodiment, as each page is moved, its page table entry is updated to point to the new location of the page so that the page is still accessible during promotion of the segment to a pre-translated segment. In this way, virtual-to-real address translation may be performed by concatenating the segment base real address, the page identifier, and a byte offset into the page.

Abstract: A mechanism for generating pre-translated segments for use in virtual to real address translation is provided in which segments that are determined to meet a density threshold are promoted to a pre-translated segment class. The pages of these segments are moved to a contiguous portion of memory and the segment table entry corresponding to the segment is updated to indicate the segment to be a pre-translated segment and to include the base real address for the contiguous portion of memory. In one embodiment, as each page is moved, its page table entry is updated to point to the new location of the page so that the page is still accessible during promotion of the segment to a pre-translated segment. In this way, virtual-to-real address translation may be performed by concatenating the segment base real address, the page identifier, and a byte offset into the page.

Abstract: Methods, systems, and computer program products are disclosed for mapping a virtual memory page to a real memory page frame in a multiprocessing environment that supports a multiplicity of operating system images. Typical embodiments include retrieving into an operating system image, from memory accessible to a multiplicity of operating system images, a most recently used cache color for a cache, where the cache is shared by the operating system image with at least one other operating system image; selecting a new cache color in dependence upon the most recently used cache color; selecting in the operating system image a page frame in dependence upon the new cache color; and storing in the memory the new cache color as the most recently used cache color for the cache.

Abstract: A control mechanism that allows individual applications to turn hardware prefetch on or off is provided. By preliminary trial run one can determine precisely whether an application will benefit or suffer from hardware prefetch. The selective control of prefetching by individual applications is made possible by associating a status bit with individual processes in the machine status word of each processor. Using this prefetch bit, a process turns prefetching on or off to its own advantage in the processor core immediately after a context switch.

Abstract: A method, system, and program for dynamic memory management of unallocated memory in a logical partitioned data processing system. A logical partitioned data processing system typically includes multiple memory units, processors, I/O adapters, and other resources enabled for allocation to multiple logical partitions. A partition manager operating within the data processing system manages allocation of the resources to each logical partition. In particular, the partition manager manages allocation of a first portion of the multiple memory units to at least one logical partition. In addition, the partition manager manages a memory pool of unallocated memory from among the multiple memory units. Responsive to receiving a request for a memory loan from one of the allocated logical partitions, a second selection of memory units from the memory pool is loaned to the requesting logical partition.

Abstract: Methods, systems, and computer program products are disclosed for mapping a virtual memory page to a real memory page frame in a multiprocessing environment that supports a multiplicity of operating system images. Typical embodiments include retrieving into an operating system image, from memory accessible to a multiplicity of operating system images, a most recently used cache color for a cache, where the cache is shared by the operating system image with at least one other operating system image; selecting a new cache color in dependence upon the most recently used cache color; selecting in the operating system image a page frame in dependence upon the new cache color; and storing in the memory the new cache color as the most recently used cache color for the cache.

Abstract: A mechanism for generating pre-translated segments for use in virtual to real address translation is provided in which segments that are determined to meet a density threshold are promoted to a pre-translated segment class. The pages of these segments are moved to a contiguous portion of memory and the segment table entry corresponding to the segment is updated to indicate the segment to be a pre-translated segment and to include the base real address for the contiguous portion of memory. In one embodiment, as each page is moved, its page table entry is updated to point to the new location of the page so that the page is still accessible during promotion of the segment to a pre-translated segment. In this way, virtual-to-real address translation may be performed by concatenating the segment base real address, the page identifier, and a byte offset into the page.

Abstract: A mechanism for generating pre-translated segments for use in virtual to real address translation is provided in which segments that are determined to meet a density threshold are promoted to a pre-translated segment class. The pages of these segments are moved to a contiguous portion of memory and the segment table entry corresponding to the segment is updated to indicate the segment to be a pre-translated segment and to include the base real address for the contiguous portion of memory. In one embodiment, as each page is moved, its page table entry is updated to point to the new location of the page so that the page is still accessible during promotion of the segment to a pre-translated segment. In this way, virtual-to-real address translation may be performed by concatenating the segment base real address, the page identifier, and a byte offset into the page.