Patents by Inventor Sujatha Sankaran
Sujatha Sankaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20080251284Abstract: An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.Type: ApplicationFiled: April 7, 2008Publication date: October 16, 2008Applicant: International Business Machines CorporationInventors: Matthew Earl Colburn, Ricardo Alves Donaton, Conal E. Murray, Satyanarayana Venkata Nitta, Sampath Purushothaman, Sujatha Sankaran, Thedorus Eduardus Fransiscus Maria Standaert, Xiao Hu Liu
-
Publication number: 20080217777Abstract: A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the dielectric material from the CMP process as well as subsequent etch, clean and deposition steps of the next interconnect level.Type: ApplicationFiled: May 20, 2008Publication date: September 11, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul S. McLaughlin, Sujatha Sankaran, Theodorus E. Standaert
-
Patent number: 7405147Abstract: A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column.Type: GrantFiled: January 30, 2004Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
-
Patent number: 7394154Abstract: A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the dielectric material from the CMP process as well as subsequent etch, clean and deposition steps of the next interconnect level.Type: GrantFiled: September 13, 2005Date of Patent: July 1, 2008Assignee: International Business Machines CorporationInventors: Paul S. McLaughlin, Sujatha Sankaran, Theodorus E. Standaert
-
Patent number: 7371684Abstract: A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.Type: GrantFiled: May 16, 2005Date of Patent: May 13, 2008Assignee: International Business Machines CorporationInventors: Matthew Earl Colburn, Ricardo Alves Donaton, Conal E. Murray, Satyanarayana Venkata Nitta, Sampath Purushothaman, Sujatha Sankaran, Theodorus Eduardus Fransiscus Maria Standaert, Xiao Hu Liu
-
Publication number: 20080088027Abstract: A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.Type: ApplicationFiled: November 29, 2007Publication date: April 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: THEODORUS STANDAERT, WILLIAM BREARLEY, STEPHEN GRECO, SUJATHA SANKARAN
-
Publication number: 20080038915Abstract: Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.Type: ApplicationFiled: August 31, 2007Publication date: February 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel EDELSTEIN, Matthew COLBURN, Edward COONEY, Timothy DALTON, John FITZSIMMONS, Jeffrey GAMBINO, Elbert HUANG, Michael LANE, Vincent MCGAHAY, Lee NICHOLSON, Satyanarayana NITTA, Sampath PURUSHOTHAMAN, Sujatha SANKARAN, Thomas SHAW, Andrew SIMON, Anthony STAMPER
-
Publication number: 20080038923Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.Type: ApplicationFiled: September 6, 2007Publication date: February 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel EDELSTEIN, Matthew COLBURN, Edward COONEY, Timothy DALTON, John FITZSIMMONS, Jeffrey GAMBINO, Elbert HUANG, Michael LANE, Vincent MCGAHAY, Lee NICHOLSON, Satyanarayana NITTA, Sampath PURUSHOTHAMAN, Sujatha SANKARAN, Thomas SHAW, Andrew SIMON, Anthony STAMPER
-
Publication number: 20080026568Abstract: A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.Type: ApplicationFiled: July 31, 2006Publication date: January 31, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodorus Eduardus Standaert, Pegeen M. Davis, John Anthony Fitzsimmons, Stephen Edward Greco, Tze-Man Ko, Naftali Eliahu Lustig, Lee Matthew Nicholson, Sujatha Sankaran
-
Patent number: 7323410Abstract: A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.Type: GrantFiled: August 8, 2005Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: Theodorus E. Standaert, William H. Brearley, Stephen E. Greco, Sujatha Sankaran
-
Publication number: 20070232048Abstract: A method and apparatus is provided for fabricating a damascene interconnection. The method begins by forming on a substrate an organosilicate dielectric layer, a capping layer on the organosilicate dielectric layer, and a resist pattern over the capping layer to define a first interconnect opening. The capping layer is etched through the resist pattern using a first etchant. The resist pattern is removed after etching the capping layer. The dielectric layer is etched through the capping layer using a second etchant different from the first etchant to form the first interconnect opening. An interconnection is completed by filling the first interconnect opening with conductive material.Type: ApplicationFiled: March 31, 2006Publication date: October 4, 2007Inventors: Koji Miyata, Sujatha Sankaran, Theodorus Eduardus Standaert, Ricardo Donaton
-
Publication number: 20070057374Abstract: A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the dielectric material from the CMP process as well as subsequent etch, clean and deposition steps of the next interconnect level.Type: ApplicationFiled: September 13, 2005Publication date: March 15, 2007Applicant: International Business Machines CorporationInventors: Paul McLaughlin, Sujatha Sankaran, Theodorus Standaert
-
Publication number: 20070032055Abstract: A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.Type: ApplicationFiled: August 8, 2005Publication date: February 8, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodorus Standaert, William Brearley, Stephen Greco, Sujatha Sankaran
-
Publication number: 20060258159Abstract: A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.Type: ApplicationFiled: May 16, 2005Publication date: November 16, 2006Applicant: International Business Machines CorporationInventors: Matthew Colburn, Ricardo Donaton, Conal Murray, Satyanarayana Nitta, Sampath Purushothaman, Sujatha Sankaran, Theodorus Eduardus Fransiscus Standaert, Xiao Liu
-
Publication number: 20050167838Abstract: A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column.Type: ApplicationFiled: January 30, 2004Publication date: August 4, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel Edelstein, Matthew Colburn, Edward Cooney, Timothy Dalton, John Fitzsimmons, Jeffrey Gambino, Elbert Huang, Michael Lane, Vincent McGahay, Lee Nicholson, Satyanarayana Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas Shaw, Andrew Simon, Anthony Stamper