Patents by Inventor Sujea Lim

Sujea Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10248183
    Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Jennifer Chin, Su Wei Lim, Poh Thiam Teoh, Ting Lok Song, Sun Zheng E, Say Cheong Gan, Sujea Lim, Ming Yi Lim
  • Publication number: 20170083079
    Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.
    Type: Application
    Filed: December 6, 2016
    Publication date: March 23, 2017
    Applicant: Intel Corporation
    Inventors: Jennifer Chin, Su Wei Lim, Poh Thiam Teoh, Ting Lok Song, Sun Zheng E, Say Cheong Gan, Sujea Lim, Ming Yi Lim
  • Patent number: 9563256
    Abstract: Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing unit (CPU) to the root port; identifying a power up activity for the CPU; and triggering an exit flow for a power state in conjunction with sending a second downstream cycle to the root port. In more particular embodiments, the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion. In addition, a prewake indicator can be sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: February 7, 2017
    Assignee: Intel Corporation
    Inventors: Sun Zheng E, Ting Lok Song, Poh Thiam Teoh, Jennifer Chin, Say Cheong Gan, Sujea Lim, Su Wei Lim
  • Patent number: 9558030
    Abstract: Methods, apparatuses, and systems for handling transactions received after a configuration request, the method, for example, comprising: receiving a configuration change request by a transaction-handling logic block; performing a configuration change by the transaction-handling logic block in response to the configuration change request, wherein the logic block is to handle transactions received prior to receipt of the configuration change request differently than transactions received after receipt of the configuration change request; receiving, by the transaction-handling logic block, a first transaction before receiving the configuration change request; receiving, by the transaction-handling logic block, a second transaction after receiving the configuration change request and before the configuration change is complete; differentiating the first transaction from the second transaction based on the order in which the first and second transactions were received relative to receipt of the configuration chang
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: January 31, 2017
    Assignee: Intel Corporation
    Inventors: Su Wei Lim, Kah Meng Yeem, Poh Thiam Teoh, Hooi Kar Loo, Sujea Lim
  • Patent number: 9513662
    Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: December 6, 2016
    Assignee: Intel Corporation
    Inventors: Jennifer Chin, Su Wei Lim, Poh Thiam Teoh, Ting Lok Song, Sun Zheng E, Say Cheong Gan, Sujea Lim, Ming Yi Lim
  • Publication number: 20140195835
    Abstract: Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing unit (CPU) to the root port; identifying a power up activity for the CPU; and triggering an exit flow for a power state in conjunction with sending a second downstream cycle to the root port. In more particular embodiments, the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion. In addition, a prewake indicator can be sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Inventors: Sun Zheng E., Ting Lok Song, Poh Thiam Teoh, Jennifer Chin, Say Cheong Gan, Sujea Lim, Su Wei Lim
  • Publication number: 20140195830
    Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Inventors: Jennifer Chin, Su Wei Lim, Poh Thiam Teoh, Ting Lok Song, Sun Zheng E, Say Cheong Gan, Sujea Lim, Ming Yi Lim
  • Publication number: 20130275985
    Abstract: Methods, apparatuses, and systems for handling transactions received after a configuration request, the method, for example, comprising: receiving a configuration change request by a transaction-handling logic block; performing a configuration change by the transaction-handling logic block in response to the configuration change request, wherein the logic block is to handle transactions received prior to receipt of the configuration change request differently than transactions received after receipt of the configuration change request; receiving, by the transaction-handling logic block, a first transaction before receiving the configuration change request; receiving, by the transaction-handling logic block, a second transaction after receiving the configuration change request and before the configuration change is complete; differentiating the first transaction from the second transaction based on the order in which the first and second transactions were received relative to receipt of the configuration chang
    Type: Application
    Filed: November 9, 2011
    Publication date: October 17, 2013
    Applicant: INTEL CORPORATION
    Inventors: Su Wei Lim, Kah Meng Yeem, Poh Thiam Teoh, Hooi Kar Loo, Sujea Lim