Patents by Inventor Sujit Sharan

Sujit Sharan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031288
    Abstract: Integrated passive components in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die including a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Sujit Sharan, Ravindranath Mahajan, Stefan Rusu, Donald S. Gardner
  • Publication number: 20210134726
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Application
    Filed: January 7, 2021
    Publication date: May 6, 2021
    Inventors: Henning BRAUNISCH, Chia-Pin CHIU, Aleksandar ALEKSOV, Hinmeng AU, Stefanie M. LOTZ, Johanna M. SWAN, Sujit SHARAN
  • Publication number: 20210125942
    Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.
    Type: Application
    Filed: January 6, 2021
    Publication date: April 29, 2021
    Inventors: Dae-Woo KIM, Sujit SHARAN, Sairam AGRAHARAM
  • Patent number: 10978423
    Abstract: A package assembly includes a substrate extending from a first substrate end to a second substrate end. A plurality of conductive traces extend along the substrate. A plurality of contacts are coupled with the respective conductive traces of the plurality of conductive traces. Each of the contacts of the plurality of contacts includes a contact pad coupled with a respective conductive trace of the plurality of conductive traces, and a contact post coupled with the contact pad, the contact post extends from the contact pad. A package cover layer is coupled over the plurality of contact posts. The plurality of contact posts are configured to penetrate the package cover layer and extend to a raised location above the package cover layer.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Sujit Sharan, Ravindranath V. Mahajan
  • Patent number: 10923429
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz, Johanna M. Swan, Sujit Sharan
  • Publication number: 20210043588
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an article having a substrate, a semiconductor die thereon, a routing carrier attached to the substrate, and a transmission pathway electrically connected to the semiconductor die and the substrate, wherein the transmission pathway runs through the routing carrier. In selected examples, the article is made by manufacturing a substrate, attaching a semiconductor die to the substrate, fabricating a routing carrier comprising a transmission pathway, and integrating the routing carrier into the substrate.
    Type: Application
    Filed: August 9, 2019
    Publication date: February 11, 2021
    Inventors: Lijiang Wang, Jianyong Xie, Sujit Sharan, Robert L. Sankman
  • Patent number: 10916514
    Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Sujit Sharan, Sairam Agraharam
  • Publication number: 20200402940
    Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 24, 2020
    Inventors: Dae-Woo KIM, Ajay JAIN, Neha M. PATEL, Rodrick J. HENDRICKS, Sujit SHARAN
  • Publication number: 20200395300
    Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly including a substrate having a conductive plane; and a bridge having first contacts at a first surface and second contacts at an opposing second surface, wherein the bridge is embedded in the substrate and coupled to the conductive plane in the substrate via the first contacts, wherein the bridge is coupled to a first die and a second die via the second contacts, and wherein the bridge does not include a silicon substrate.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Applicant: Intel Corporation
    Inventors: Biancun Xie, Jianyong Xie, Sujit Sharan, Debendra Mallik, Robert L. Sankman
  • Publication number: 20200381350
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 3, 2020
    Inventors: Sujit SHARAN, Kemal AYGUN, Zhiguo QIAN, Yidnekachew MEKONNEN, Zhichao ZHANG, Jianyong XIE
  • Publication number: 20200373235
    Abstract: Embodiments herein relate to systems, apparatuses, or processes for an interconnect hub for dies that includes a first side and a second side opposite the first side to couple with three or more dies, where the second side includes a plurality of electrical couplings to electrically couple at least one of the three or more dies to another of the three or more dies to facilitate data transfer between at least a subset of the three or more dies. The three or more dies may be tiled dies.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 26, 2020
    Inventors: Andrew COLLINS, Sujit SHARAN, Jianyong XIE
  • Publication number: 20200357747
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Henning BRAUNISCH, Chia-Pin CHIU, Aleksandar ALEKSOV, Hinmeng AU, Stefanie M. LOTZ, Johanna M. SWAN, Sujit SHARAN
  • Publication number: 20200343202
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.
    Type: Application
    Filed: April 24, 2019
    Publication date: October 29, 2020
    Inventors: Lijiang WANG, Jianyong XIE, Arghya SAIN, Xiaohong JIANG, Sujit SHARAN, Kemal AYGUN
  • Patent number: 10797014
    Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Ajay Jain, Neha M. Patel, Rodrick J. Hendricks, Sujit Sharan
  • Publication number: 20200286814
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 10, 2020
    Inventors: Ravindranath MAHAJAN, Debendra MALLIK, Sujit SHARAN, Digvijay RAORANE
  • Patent number: 10763216
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz, Johanna M. Swan, Sujit Sharan
  • Publication number: 20200235048
    Abstract: A micro-trace containing package substrate provides a low-inductance alternating-current decoupling path between a semiconductive device and a die-side capacitor.
    Type: Application
    Filed: April 2, 2020
    Publication date: July 23, 2020
    Inventors: Andrew Collins, Jianyong Xie, Sujit Sharan
  • Patent number: 10651117
    Abstract: A micro-trace containing package substrate provides a low-inductance alternating-current decoupling path between a semiconductive device and a die-side capacitor.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Andrew Collins, Jianyong Xie, Sujit Sharan
  • Publication number: 20200075493
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Application
    Filed: November 7, 2019
    Publication date: March 5, 2020
    Inventors: Henning BRAUNISCH, Chia-Pin CHIU, Aleksandar ALEKSOV, Hinmeng AU, Stefanie M. LOTZ, Johanna M. SWAN, Sujit SHARAN
  • Publication number: 20200013734
    Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Inventors: Dae-Woo KIM, Sujit SHARAN, Sairam AGRAHARAM