Patents by Inventor Sujith Kumar Billa

Sujith Kumar Billa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250080128
    Abstract: A DAC cell circuit includes: at least a DAC cell, including: a first MOSFET having a drain coupled to a first switch for receiving a first current and coupled to a second switch for generating a second current, a source coupled to ground, and a gate coupled to a first bias voltage; a capacitor coupled between the gate and the drain of the first MOSFET; and a dead-band switch coupled between the gate of the first MOSFET and the bias node. The dead-band switch is controlled by a signal which is periodic with respect to a frequency equal to an input data rate of the DAC cell, and the dead-band switch is open during a data transition.
    Type: Application
    Filed: September 3, 2024
    Publication date: March 6, 2025
    Applicant: MEDIATEK INC.
    Inventors: SUJITH KUMAR BILLA, Sung-Han Wen
  • Patent number: 12160206
    Abstract: The present invention provides an amplifier circuit, wherein the amplifier circuit includes an input terminal, a capacitor, an amplifier, a feedback circuit and an aliasing tone cancellation circuit. The input terminal is configured to receive a first input signal. The capacitor is coupled to the input terminal. The amplifier is configured to receive the input signal through the capacitor to generate an output signal. The feedback circuit is coupled between an input node and an output node of the amplifier, and is configured to generate a feedback signal according to the output signal, wherein the feedback circuit includes a storage block including a switched-capacitor. The aliasing tone cancellation circuit is coupled between the input terminal of the amplifier circuit and the input node of the amplifier, and configured to generate a signal to cancel or reduce an aliasing tone of the feedback signal according to the input signal.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: December 3, 2024
    Assignee: MEDIATEK INC.
    Inventors: Sujith Kumar Billa, Sung-Han Wen
  • Publication number: 20220407476
    Abstract: The present invention provides an amplifier circuit, wherein the amplifier circuit includes an input terminal, a capacitor, an amplifier, a feedback circuit and an aliasing tone cancellation circuit. The input terminal is configured to receive a first input signal. The capacitor is coupled to the input terminal. The amplifier is configured to receive the input signal through the capacitor to generate an output signal. The feedback circuit is coupled between an input node and an output node of the amplifier, and is configured to generate a feedback signal according to the output signal, wherein the feedback circuit includes a storage block including a switched-capacitor. The aliasing tone cancellation circuit is coupled between the input terminal of the amplifier circuit and the input node of the amplifier, and configured to generate a signal to cancel or reduce an aliasing tone of the feedback signal according to the input signal.
    Type: Application
    Filed: May 23, 2022
    Publication date: December 22, 2022
    Applicant: MEDIATEK INC.
    Inventors: Sujith Kumar Billa, Sung-Han Wen