Abstract: The present invention relates to a method for manufacturing a reflective multi-layered thin film mirror for an extreme ultraviolet radiation (EUV) exposure process that is one of the next generation exposure process masks using an atomic force microscope (AFM). This reflective multi-layered thin film mirror for extreme ultraviolet radiation (EUV) exposure process allows metal oxide structures with fixed height and width to be obtained using anodic oxidization phenomenon between the cantilever tip of a atomic force microscope and an absorber material during the patterning of an absorber layer on a multi-layered thin film of a substrate, followed by forming the ultra-fine line width absorber patterns via etching of the metal oxide structure.

Abstract: Disclosed are a chip scale package and a method of fabricating the chip scale package. The chip scale package comprises conductive layers with a designated depth formed on an upper and a lower surfaces of a chip, and electrode surfaces formed on the same side surfaces of the conductive layers, which are connected to corresponding connection pads of a printed circuit board. The chip scale package is miniaturized in the whole package size. Further, the method of fabricating the chip scale package does not require a wire-bonding step or a via hole forming step, thereby simplifying the fabrication process of the chip scale package and improving the reliability of the chip scale package.

Abstract: Disclosed are a chip scale package and a method of fabricating the chip scale package. The chip scale package comprises an insulating layer formed on the upper surface of a chip provided with a plurality of terminals on its one surface, a plurality of conductive layers formed on the insulating layer and spaced from each other by a designated distance so as to be connected to each of a plurality of the terminals, and a plurality of electrode surfaces formed on each of the upper surfaces of a plurality of the conductive layers. The chip scale package is miniaturized in the whole package size. Further, the method of fabricating the chip scale package does not require a wire-bonding step or a via hole forming step, thereby simplifying the fabrication process of the chip scale package and improving the reliability of the chip scale package.