Abstract: An apparatus for processing a digital image signal includes a pseudo-luminance generator configured to generate pseudo-luminance signals from the image signal. An edge detector detects an edge in the image signal using a part of an interpolated image signal as a luminance signal for a line of the image signal including a pixel subjected to edge detection and using the pseudo-luminance signals for adjacent lines. A color suppressor suppresses pseudo-color present in the chrominance component of the image signal in response to a detected edge. A compensator may be provided to generate a second edge metric relative to the image signal to compensate for an edge detection error occurring in the edge detector. A color suppression coefficient calculator to generate a color suppression coefficient using a first edge metric generated by the edge detector and the second edge metric. Corresponding systems and methods are disclosed.

Abstract: An apparatus for processing a digital image signal includes a pseudo-luminance generator configured to generate pseudo-luminance signals from the image signal. An edge detector detects an edge in the image signal using a part of an interpolated image signal as a luminance signal for a line of the image signal including a pixel subjected to edge detection and using the pseudo-luminance signals for adjacent lines. A color suppressor suppresses pseudo-color present in the chrominance component of the image signal in response to a detected edge. A compensator may be provided to generate a second edge metric relative to the image signal to compensate for an edge detection error occurring in the edge detector. A color suppression coefficient calculator to generate a color suppression coefficient using a first edge metric generated by the edge detector and the second edge metric. Corresponding systems and methods are disclosed.

Abstract: In a synchronizer for multi-rate input data, a unified FIFO (first-in-first-out) memory receives multi-rate input data, converts the multi-rate input data into a single system operation frequency, and outputs converted data of a plurality of channels of the multi-rate input data, based on the control of a controller.

Abstract: An apparatus and method for implementing picture-in-picture with frame rate conversion includes an input buffer unit, a data synchronizing unit, first through third memories, and a memory control unit. The input buffer unit buffers input data and outputs buffered data as first data and first data enabling signals. The data synchronizing unit synchronizes the first data output with an output clock signal and outputs synchronized data as second data and second data enabling signals. The first memory multiplexes the second data and outputs stored data in response to a first memory enabling signal. The second memory writes and reads data output from the first memory in response to a frame buffer control signal. The third memory outputs stored data as a display signal. The memory control unit controls data flow between the memories and frame rates of the input data.

Abstract: Provided is a progressive scan method used in a display using adaptive edge interpolation. According to the progressive scan method, a final edge direction that satisfies a first edge-determination condition and a second edge-determination condition is detected by performing interpolation for 7×3 pixel windows, using code determination and a comparison of a standard deviation based on differences between luminances of pixel data divided by an edge boundary. As a result, directional edge interpolation is carried out in a region of a low gradient below 45° and to 27° at the minimum, and simple intra-field linear interpolation can be performed in a high-frequency texture region. Subsequently, it is possible to remove high-frequency noise introduced in edge dependent interpolation or unnatural screen display due to zigzagged edges, thereby improving the quality of a display.

Abstract: Deinterlacing apparatus and method capable of outputting two consecutive deinterlaced frames include a field buffer, a shift buffer, a frame generator, and a line exchanger. The field buffer receives and stores a plurality of consecutive interlaced fields, and then outputs, in response to a control signal, p-th interlaced line data of an m-th field, p-th interlaced line data of an (m+2)-th field, p-th interlaced line data of an (m+1)-th field, and (p+1)-th interlaced line data of the (m+1)-th field in series or the p-th interlaced line data of the (m+1)-th field, p-th interlaced line data of an (m+3)-th field, the p-th interlaced line data of the (m+2)-th field, and (p+1)-th interlaced line data of the (m+2)-th field in series. The shift buffer which receives signals output from the field buffer in series, converts the signals into parallel signals, and outputs first through fourth line data in parallel.

Abstract: Provided is a progressive scan method used in a display using adaptive edge interpolation. According to the progressive scan method, a final edge direction that satisfies a first edge-determination condition and a second edge-determination condition is detected by performing interpolation for 7×3 pixel windows, using code determination and a comparison of a standard deviation based on differences between luminances of pixel data divided by an edge boundary. As a result, directional edge interpolation is carried out in a region of a low gradient below 45° and to 27° at the minimum, and simple intra-field linear interpolation can be performed in a high-frequency texture region. Subsequently, it is possible to remove high-frequency noise introduced in edge dependent interpolation or unnatural screen display due to zigzagged edges, thereby improving the quality of a display.

Abstract: Deinterlacing apparatus and method capable of outputting two consecutive deinterlaced frames include a field buffer, a shift buffer, a frame generator, and a line exchanger. The field buffer receives and stores a plurality of consecutive interlaced fields, and then outputs, in response to a control signal, p-th interlaced line data of an m-th field, p-th interlaced line data of an (m+2)-th field, p-th interlaced line data of an (m+1)-th field, and (p+1)-th interlaced line data of the (m+1)-th field in series or the p-th interlaced line data of the (m+1)-th field, p-th interlaced line data of an (m+3)-th field, the p-th interlaced line data of the (m+2)-th field, and (p+1)-th interlaced line data of the (m+2)-th field in series. The shift buffer which receives signals output from the field buffer in series, converts the signals into parallel signals, and outputs first through fourth line data in parallel.

Abstract: An image processing apparatus and a method for implementing picture-in-picture with frame rate conversion are provided. The image processing apparatus includes an input buffer unit, a data synchronizing unit, first through third memories, and a memory control unit. The input buffer unit buffers input data which are externally and asynchronously input through two or more channels by different input clock signals and outputs buffered data as first data and first data enabling signals. The data synchronizing unit synchronizes the first data output from the input buffer unit with an output clock signal in response to the input clock signals and the first data enabling signals and outputs synchronized data as second data and second data enabling signals in response to each of the first data enabling signals. The first memory multiplexes the second data according to time sharing, stores the second data in different regions, and outputs stored data in response to a first memory enabling signal.