Abstract: A single chip multiprocessing microprocessor having a synchronization register file is disclosed. This microprocessor includes a plurality of ILP (Instruction Level Parallelism) processors connecting through an internal bus, and a synchronization register file having a multiport so that the ILP processors concurrently access for thereby performing atomic instructions for thereby enhancing the performance of single chip multiprocessing microprocessor and a system using the same by processing atomic instruction without memory access when performing synchronization among internal processors.

Abstract: The present invention relates to a node connection apparatus. The 3-link node interconnection apparatus and parallel processing apparatus using the same confirm expanding nodes freely, only using fixed three connecting links, and are suitable to normal packaging method because of easy dividing into 2n (n>1) nodes. The apparatuses comprise the following nodes. The first node has three links connected to other nodes respectively. The second node has three links, one links of them is connected to the first node, and the other two links are in charge of connection of X+ direction, X− direction. The third node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Y+ direction, Y− direction. The fourth node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Z+ direction, Z− direction.

Abstract: An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.

Abstract: The present invention relates to a routing control apparatus for performing a round robin arbitration and an adaptive routing control. The present invention relates to a routing controller for performing an arbitration and a routing control which are nucleus functions of the crossbar routing switch and, in particular, to a normal routing controller unit for performing a priority based round robin arbitration and an adaptive routing controller unit for performing an adaptive routing control by adding an adaptive routing switch logic to the normal routing controller.

Abstract: A broadcast transfer method for transferring the same data from any one node of the interconnection network of the parallel processing computer to every other nodes. The object of the present invention is to provide a broadcast transfer method for a hierarchical interconnection network with multiple tags which can be easily expanded, wherein each switch can perform a routing control function, and which enables the same packet to be transferred irrespective of the receiving group of each layer even when multiple tags are used in the same manner as in the point-to-point packet transfer.

Abstract: There is disclosed a node booting method in a high-speed parallel computer. Other than the method in which the system using a conventional network down loads the operating system kernel image from the boot server, the method according to the present invention provides an environment by which a boot can be progressed in parallel and a boot progress state can be monitored through a console terminal, thus improving a boot speed.

Abstract: The present invention relates to a structure of processor having a plurality of main processors and sub processors, and a method for sharing the sub processors, wherein a method is used for preserving a state of a register file by using a shadow register file when main processor inputs an instruction of the sub processor in case that an exceptional situation happens under processing of an instruction of sub processor and for rolling back thereafter the preserved state in case there is an information of occurrence of the exceptional situation from the sub processor. Also, in order to solve a problem that cache efficiency is reduced due to the use of a first cache which is relatively small and frequently used, there is suggested a first cache bypassing function. Further, in order to solve a problem that its processing speed is reduced when the main processor transfers instructions in sub processor, it is possible to improve the processors' parallelism and its efficiency by providing an extra register file.

Abstract: The present invention relates to a message-passing computer system and a packet-switched interconnection network. The message transfer apparatus in a packet-switched interconnection network includes a message send controller controlling a send procedure in which messages requested by a processor are sent via an output port, and a timer enabled by an output signal of the message send controller and generating a timeout signal. A buffer unit is connected to the message send controller and is composed of a message buffer having four buffers and a data buffer. A local bus controller connects the message send controller and the buffer unit to the local bus and controls a transfer request and a transfer response to the local bus. An output port controller connected to both the message send controller and the buffer unit controls the output port which sends a packet to an interconnection network.

Abstract: The present invention discloses a method for controlling a message send in a packet-switched interconnection network, which incorporates a message send controller supporting an efficient message send and a dedicated hardware capable of maximizing a message send rate, taking the structural characteristics of the message-passing parallel computer system method into maximum considerations, thereby minimizing software and hardware overhead in sending a message and being capable of selecting a message send method in accordance with the message characteristics.

Abstract: A message-passing multiprocessor system, such as, a network interface, a method for transferring messages between a node and a node, and a method for formatting the same in a message-passing computer system are disclosed herein. In the network interface for a computer system there are a plurality of nodes connected with one another through an interconnection network for communicating messages, and more than one processor, and a local shared memory, which are connected with one another through a node bus.

Abstract: A non-blocking fault tolerant gamma network for a multi-processor system is disclosed, including: N dual links respectively connected to n source nodes, and for transmitting data input; a first stage made up with n 2.times.3 switching devices for outputting data transmitted from the N dual links; a second stage made up with n 3.times.4 switching devices for outputting data output from the first stage; a third stage to n-1 stage made up with (n-2).times.N 4.times.4 switching devices for receiving data output from the second stage at the third stage and outputting the data to n-1 stage; an n stage made up with n 4.times.

Abstract: A memory data path controller for a large-scale parallel processing computer system in which, when a network interface and bus interface request access to a single-port memory, a dual path controller dividedly stores memory access requests in network queue and bus queue. This allows a single-port DRAM to be used as a dual-port memory device. Further, the network queue and bus queue are multi-staged to store sequential memory requests and transmit reading/writing data of the network queue or bus queue to the DRAM memory.