Abstract: A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.

Abstract: Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially exposing the conductive pattern. An oxide layer is formed on substantially the entire surface of the substrate on which the opening is formed. A reduction process is performed to reduce the oxide layer. Here, the oxide layer on a bottom region of the opening is reduced to a catalyst layer, and the oxide layer on a region other than the bottom region of the opening is reduced to a non-catalyst layer. A nano material is grown from the catalyst layer, so that a contact plug is formed in the opening.

Abstract: A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.

Abstract: Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially exposing the conductive pattern. An oxide layer is formed on substantially the entire surface of the substrate on which the opening is formed. A reduction process is performed to reduce the oxide layer. Here, the oxide layer on a bottom region of the opening is reduced to a catalyst layer, and the oxide layer on a region other than the bottom region of the opening is reduced to a non-catalyst layer. A nano material is grown from the catalyst layer, so that a contact plug is formed in the opening.

Abstract: Methods of forming phase-changeable memory devices include techniques to inhibit void formation in phase-changeable materials in order to increase device reliability. These techniques to inhibit void formation use an electrically insulating growth-inhibiting layer to guide the formation of a phase-changeable material region within a memory cell (e.g., PRAM cell). In particular, methods of forming an integrated circuit memory device include forming an interlayer insulating layer having an opening therein, on a substrate, and then lining sidewalls of the opening with a seed layer (i.e., growth-enhancing layer) that supports growth of a phase-changeable material thereon. An electrically insulating growth-inhibiting layer is then selectively formed on a portion of the interlayer insulating layer surrounding the opening. The formation of the growth-inhibiting layer is followed by a step to selectively grow a phase-changeable material region in the opening, but not on the growth-inhibiting layer.

Abstract: A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

Abstract: Methods of forming phase-changeable memory devices include techniques to inhibit void formation in phase-changeable materials in order to increase device reliability. These techniques to inhibit void formation use an electrically insulating growth-inhibiting layer to guide the formation of a phase-changeable material region within a memory cell (e.g., PRAM cell). In particular, methods of forming an integrated circuit memory device include forming an interlayer insulating layer having an opening therein, on a substrate, and then lining sidewalls of the opening with a seed layer (i.e., growth-enhancing layer) that supports growth of a phase-changeable material thereon. An electrically insulating growth-inhibiting layer is then selectively formed on a portion of the interlayer insulating layer surrounding the opening. The formation of the growth-inhibiting layer is followed by a step to selectively grow a phase-changeable material region in the opening, but not on the growth-inhibiting layer.

Abstract: Disclosed are a semiconductor device and a related method of manufacture. The semiconductor device comprises a semiconductor substrate, a conductive structure including contact regions and gate structures formed on the semiconductor substrate, a protection layer formed on the gate structures, an insulation layer formed on the protection layer, and a plurality of contacts directly contacting the contact regions and the semiconductor substrate through the insulation layer, wherein the contacts have substantially different heights from each other.

Abstract: A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

Abstract: In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to contact the lower electrode pattern and the interlayer insulating layer; and an upper electrode on the phase changeable pattern.

Abstract: A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

Abstract: A semiconductor memory device and a method for forming the same. The method includes forming an insulating layer on a semiconductor substrate having a conductive region, forming a contact hole that exposes the conductive region by etching the insulating layer, forming a barrier metal layer that covers a sidewall and a bottom of the contact hole, and forming a contact plug in the contact hole by interposing the barrier metal layer therebetween. An etching process may be preformed that recesses the barrier metal layer and the contact plug in such a manner that a top surface of the contact plug protrudes upward beyond a top surface of the barrier metal layer. A capping plug may be formed covering the recessed barrier metal layer and the recessed contact plug. A capacitor may be formed on the capping plug.

Abstract: In a method of manufacturing a ferroelectric capacitor, a lower electrode layer is formed on a substrate. The lower electrode layer includes at least one lower electrode film. A ferroelectric layer is formed on the lower electrode layer, and then an upper electrode layer is formed on the ferroelectric layer. A hard mask structure is formed on the upper electrode layer. The hard mask structure includes a first hard mask and a second hard mask. An upper electrode, a ferroelectric layer pattern and a lower electrode are formed by partially etching the upper electrode layer, the ferroelectric layer and the lower electrode layer using the hard mask structure. The hard mask structure may prevent damage to the ferroelectric layer and may enlarge an effective area of the ferroelectric capacitor so that the ferroelectric capacitor may have enhanced electrical and ferroelectric characteristics.

Abstract: Disclosed are a semiconductor device and a related method of manufacture. The semiconductor device comprises a semiconductor substrate, a conductive structure including contact regions and gate structures formed on the semiconductor substrate, a protection layer formed on the gate structures, an insulation layer formed on the protection layer, and a plurality of contacts directly contacting the contact regions and the semiconductor substrate through the insulation layer, wherein the contacts have substantially different heights from each other.

Abstract: A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

Abstract: In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to contact the lower electrode pattern and the interlayer insulating layer; and an upper electrode on the phase changeable pattern.

Abstract: A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

Abstract: The present invention discloses a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes a semiconductor substrate, a capacitor lower electrode, a ferroelectric layer, and a capacitor upper electrode. The semiconductor substrate has a lower structure. The capacitor lower electrode has a cylindrical shape and a certain height. The ferroelectric layer is conformally stacked over substantially the entire surface of the semiconductor substrate including the capacitor lower electrode. The capacitor upper electrode has a spacer shape and is formed around the sidewall of the ferroelectric layer that surrounds the lower electrode. In the method of forming the ferroelectric memory device, a semiconductor substrate having an interlayer dielectric layer and a lower electrode contact formed through the interlayer dielectric layer is prepared. A cylindrical capacitor lower electrode is formed on the interlayer dielectric layer to cover the contact.

Abstract: A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

Abstract: The present invention discloses a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes a semiconductor substrate, a capacitor lower electrode, a ferroelectric layer, and a capacitor upper electrode. The semiconductor substrate has a lower structure. The capacitor lower electrode has a cylindrical shape and a certain height. The ferroelectric layer is conformally stacked over substantially the entire surface of the semiconductor substrate including the capacitor lower electrode. The capacitor upper electrode has a spacer shape and is formed around the sidewall of the ferroelectric layer that surrounds the lower electrode. In the method of forming the ferroelectric memory device, a semiconductor substrate having an interlayer dielectric layer and a lower electrode contact formed through the interlayer dielectric layer is prepared. A cylindrical capacitor lower electrode is formed on the interlayer dielectric layer to cover the contact.