Abstract: A data compensation circuit includes a reference frame memory device which stores reference frame data, an accumulated stress memory device which stores cumulative stress data for each of pixels, a stress data generating block which compares output image data with the reference frame data to generate stress data for each of the pixels, a memory control block which adds the stress data to the cumulative stress data to update the cumulative stress data and a compensating block which generates the output image data by generating afterimage compensation data for each of the pixels based on the cumulative stress data and compensating input image data based on the afterimage compensation data.

Abstract: A display device includes: a first electrode; a pixel defining layer on the first electrode; a separation layer on the pixel defining layer; an emission structure on the first electrode and the separation layer; and a second electrode on the emission structure, wherein the separation layer comprises a first separation layer on the pixel defining layer and having a first width, and a second separation layer on the first separation layer and having a second width greater than the first width, wherein the emission structure includes a first layer having a first thickness, and a second layer having a second thickness greater than the first thickness, and wherein the second separation layer is between the first layer and the second layer.

Abstract: A display device is disclosed that includes: pixels each including emission areas and a non-emission area adjacent to the emission areas, and a pixel defining layer overlapping the non-emission area. The pixel defining layer includes trenches enclosing the respective emission areas and spaced apart from each other. A corner of each of the trenches is chamfered.

Abstract: A data compensation circuit includes a reference frame memory device which stores reference frame data, an accumulated stress memory device which stores cumulative stress data for each of pixels, a stress data generating block which compares output image data with the reference frame data to generate stress data for each of the pixels, a memory control block which adds the stress data to the cumulative stress data to update the cumulative stress data and a compensating block which generates the output image data by generating afterimage compensation data for each of the pixels based on the cumulative stress data and compensating input image data based on the afterimage compensation data.

Abstract: A display device is provided. The display device includes a first substrate, a first charge trap layer disposed on the first substrate and including silicon nitride, a semiconductor layer disposed on the first charge trap layer and including a first active layer of a first transistor and a second active layer of a second transistor, and an organic light emitting element electrically connected to the first transistor, wherein a ratio of a content of a Si element to a content of an N element in the first charge trap layer is in a range of 1.6 to 2.5.

Abstract: An embodiment of the invention provides a display device including: a substrate; a first transistor comprising a first semiconductor layer and a second transistor comprising a second semiconductor layer, the first and second semiconductor layers positioned on the substrate; a light emitting diode connected to the first transistor, wherein: the first transistor is a driving transistor; the second transistor is a switching transistor; a first concentration of fluorine included in the first semiconductor layer is higher than a second concentration of fluorine in the second semiconductor layer; and a first difference between the first and second concentrations substantially at or near a first interface of the first and second semiconductor layers is larger than a second difference between the first and second concentrations at a second interface of the first and second semiconductor layers, the second interface further from the substrate than the first interface.

Abstract: An electronic panel, includes: a base substrate including a front surface, a rear surface opposite the front surface, and a plurality of side surfaces connecting the front surface and the rear surface to each other; a pixel definition layer on the front surface of the base substrate and having a plurality of openings defined therein; a plurality of emitting elements in the openings; and a spacer on the pixel definition layer and spaced apart from the openings, wherein a thickness of the spacer is equal to or greater than a thickness of the pixel definition layer.

Abstract: A display device includes pixels. Each of the pixels includes: a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the second node; a first sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to a fourth node; and a second sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the fourth node, and a second electrode connected to the third node. A channel width of the second sub-transistor is wider than a channel width of the first sub-transistor.

Abstract: An electronic panel, includes: a base substrate including a front surface, a rear surface opposite the front surface, and a plurality of side surfaces connecting the front surface and the rear surface to each other; a pixel definition layer on the front surface of the base substrate and having a plurality of openings defined therein; a plurality of emitting elements in the openings; and a spacer on the pixel definition layer and spaced apart from the openings, wherein a thickness of the spacer is equal to or greater than a thickness of the pixel definition layer.

Abstract: A display device includes pixels. Each of the pixels includes: a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the second node; a first sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to a fourth node; and a second sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the fourth node, and a second electrode connected to the third node. A channel width of the second sub-transistor is wider than a channel width of the first sub-transistor.

Abstract: A display device includes pixels. Each of the pixels includes: a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the second node; a first sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to a fourth node; and a second sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the fourth node, and a second electrode connected to the third node. A channel width of the second sub-transistor is wider than a channel width of the first sub-transistor.

Abstract: A display device is provided. The display device includes a first substrate, a first charge trap layer disposed on the first substrate and including silicon nitride, a semiconductor layer disposed on the first charge trap layer and including a first active layer of a first transistor and a second active layer of a second transistor, and an organic light emitting element electrically connected to the first transistor, wherein a ratio of a content of a Si element to a content of an N element in the first charge trap layer is in a range of 1.6 to 2.5.

Abstract: A data compensation circuit includes a reference frame memory device which stores reference frame data, an accumulated stress memory device which stores cumulative stress data for each of pixels, a stress data generating block which compares output image data with the reference frame data to generate stress data for each of the pixels, a memory control block which adds the stress data to the cumulative stress data to update the cumulative stress data and a compensating block which generates the output image data by generating afterimage compensation data for each of the pixels based on the cumulative stress data and compensating input image data based on the afterimage compensation data.

Abstract: A display device includes pixels. Each of the pixels includes: a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the second node; a first sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to a fourth node; and a second sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the fourth node, and a second electrode connected to the third node. A channel width of the second sub-transistor is wider than a channel width of the first sub-transistor.

Abstract: An electronic panel, includes: a base substrate including a front surface, a rear surface opposite the front surface, and a plurality of side surfaces connecting the front surface and the rear surface to each other; a pixel definition layer on the front surface of the base substrate and having a plurality of openings defined therein; a plurality of emitting elements in the openings; and a spacer on the pixel definition layer and spaced apart from the openings, wherein a thickness of the spacer is equal to or greater than a thickness of the pixel definition layer.

Abstract: Provided are a thin film transistor (TFT) and a method of manufacturing the TFT. The TFT includes a substrate; a first conductive type semiconductor layer on the substrate and having a recess; second conductive type spacers at opposite side walls in the recess; a main semiconductor layer covering the first conductive type semiconductor layer and the second conductive type spacers and comprising a channel region and source and drain regions; a gate insulating layer on the main semiconductor layer; and a gate electrode on the gate insulating layer and corresponding to the recess.

Abstract: The described technology relates generally to a thin film transistor for a display device and an organic light emitting diode display device including the same.

Abstract: Provided are a thin film transistor (TFT) and a method of manufacturing the TFT. The TFT includes a substrate; a first conductive type semiconductor layer on the substrate and having a recess; second conductive type spacers at opposite side walls in the recess; a main semiconductor layer covering the first conductive type semiconductor layer and the second conductive type spacers and comprising a channel region and source and drain regions; a gate insulating layer on the main semiconductor layer; and a gate electrode on the gate insulating layer and corresponding to the recess.

Abstract: A thin film transistor includes: a semiconductor layer on a base substrate, and having a source region, a drain region, and a channel region; a gate insulating layer covering the semiconductor layer; a gate electrode on the gate insulating layer and overlapping the channel region; an interlayer insulating layer covering the gate electrode; a source electrode and a drain electrode on the interlayer insulating layer and respectively coupled to the source region and the drain region; and a temperature adjusting member configured to adjust a temperature of the channel region by heating the channel region.

Abstract: Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide optimal performance versus stability (i.e., optimal drive current versus leakage current) for logic circuits, analog devices and/or memory devices. Also disclosed are embodiments of a method of forming the integrated circuit structure embodiments. These method embodiments incorporate the use of a cap layer pullback technique on select semiconductor bodies and subsequent wet etch process so as to avoid (or at least minimize) divot formation adjacent to some but not all semiconductor bodies.