Abstract: There is provided a nonvolatile memory device having improved crack detection reliability. The nonvolatile memory device comprises word lines that extend in a first direction, cell contact plugs that are electrically connected to the word lines and extend in a second direction intersecting the first direction, a net crack detection circuit that is on the word lines and is not in contact with the word lines, and a ring crack detection circuit that is on the word lines and is not in contact with the word lines, wherein the net crack detection circuit is electrically connected to a crack detection transistor in a peripheral circuit region, the ring crack detection circuit includes a first crack detection metal wiring that extends in a third direction intersecting the first direction and the second direction, and a second crack detection metal wiring that extends in the third direction.

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

Abstract: According to some implementations of the present disclosure, a semiconductor memory device includes a semiconductor layer including a first face and a second face opposite to the first face in a first direction directed upward from the first face to the second face; a source structure including: a plate disposed on the second face of the semiconductor layer; and a plug extending from the plate through the semiconductor layer; a plurality of gate electrodes disposed on the first face of the semiconductor layer and sequentially stacked on one an other; and a channel structure that extends through the plurality of gate electrodes and that is disposed on the plug, wherein the channel structure is electrically connected to the source structure.

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

Abstract: A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate.

Abstract: The nonvolatile memory device includes a substrate including a first surface and a second surface opposite to the first surface in a first direction; a common source line on the first surface of the substrate; a plurality of word lines stacked on the common source line; a first insulating pattern spaced apart from the plurality of word lines in a second direction crossing the first direction, and in the substrate; an insulating layer on the second surface of the substrate; a first contact plug penetrating the first insulating pattern and extending in the first direction; a second contact plug penetrating the insulating layer, extending in the first direction, and connected to the first contact plug; an upper bonding metal connected to the first contact plug and connected to a circuit element; and a first input/output pad connected to the second contact plug and electrically connected to the circuit element.

Abstract: A semiconductor memory device may include a cell substrate including a cell array region and an extension region, a first mold structure on the cell substrate, a second mold structure on the first mold structure, a channel structure passing through the first and second mold structures on the cell array region, and a cell contact structure passing through the first and second mold structures on the extension region. The first mold structure and the second mold structure respectively include first gate electrodes and second gate electrodes sequentially stacked on the cell array region and stacked in a stepwise manner on the extension region. The cell contact structure includes a lower conductive pattern connected to one of the first gate electrodes, an upper conductive pattern connected to one of the second gate electrodes, and an insulating pattern separating the lower conductive pattern from the upper conductive pattern.

Abstract: A semiconductor memory device includes a first substrate including opposite first and second surfaces, a mold structure including gate electrodes stacked on the first surface of the first substrate, a channel structure through the mold structure, a first contact via penetrating the first substrate, a second substrate including opposite third and fourth surfaces, a circuit element on the third surface of the second substrate, a first through-via through the mold structure connecting the first contact via and the circuit element, the first through-via including a first conductive pattern, and a first spacer separating the first conductive pattern from the mold structure, and a second through-via through the mold structure and spaced apart from the first through-via, the second through-via including a second conductive pattern, and a second spacer separating the second conductive pattern from the first substrate and the mold structure.

Abstract: A semiconductor memory device includes a first substrate including opposite first and second surfaces, a mold structure including gate electrodes stacked on the first surface of the first substrate, a channel structure through the mold structure, a first contact via penetrating the first substrate, a second substrate including opposite third and fourth surfaces, a circuit element on the third surface of the second substrate, a first through-via through the mold structure connecting the first contact via and the circuit element, the first through-via including a first conductive pattern, and a first spacer separating the first conductive pattern from the mold structure, and a second through-via through the mold structure and spaced apart from the first through-via, the second through-via including a second conductive pattern, and a second spacer separating the second conductive pattern from the first substrate and the mold structure.

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

Abstract: The nonvolatile memory device includes a substrate including a first surface and a second surface opposite to the first surface in a first direction; a common source line on the first surface of the substrate; a plurality of word lines stacked on the common source line; a first insulating pattern spaced apart from the plurality of word lines in a second direction crossing the first direction, and in the substrate; an insulating layer on the second surface of the substrate; a first contact plug penetrating the first insulating pattern and extending in the first direction; a second contact plug penetrating the insulating layer, extending in the first direction, and connected to the first contact plug; an upper bonding metal connected to the first contact plug and connected to a circuit element; and a first input/output pad connected to the second contact plug and electrically connected to the circuit element.

Abstract: A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate.

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

Abstract: A flash memory device, including a cell array region where a plurality of memory cells are connected in series to a single cell string, the cell array region including a pocket p-well configured to accommodate the plurality of memory cells and an n-well configured to surround the pocket p-well, a first peripheral region where low-voltage (LV) and high-voltage (HV) switches are connected to the memory cells through a word line, and a second peripheral region where bulk voltage switches are connected to bulk regions of the LV and HV switches.

Abstract: A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.

Abstract: A method of forming a semiconductor device pattern, a method of forming a charge storage pattern, a non-volatile memory device including a charge storage pattern and a method of manufacturing the same are provided. The method of forming the charge storage pattern including forming a trench on a substrate, and a device isolation pattern in the trench. The device isolation pattern protrudes from a surface of the substrate such that an opening exposing the substrate is formed. A tunnel oxide layer is formed on the substrate in the opening. A preliminary charge storage pattern is formed on the tunnel oxide layer and the device isolation pattern by selective deposition of conductive materials. The preliminary charge storage pattern may be removed from the device isolation pattern. The preliminary charge storage pattern remains only on the tunnel oxide layer to form the charge storage pattern on the substrate.

Abstract: A non-volatile memory device includes a substrate and a tunnel insulation layer pattern, such that each portion of the tunnel insulation pattern extends along a first direction and adjacent portions of the tunnel insulation layer pattern may be separated in a second direction that is substantially perpendicular to the first direction. A non-volatile memory device may include a gate structure formed on the tunnel insulation layer pattern. The gate structure may include a floating gate formed on the tunnel insulation layer pattern along the second direction, a first conductive layer pattern formed on the floating gate in the second direction, a dielectric layer pattern formed on the first conductive layer pattern along the second direction, and a control gate formed on the dielectric layer pattern in the second direction.