Patents by Inventor Suk-Kyu Ryu

Suk-Kyu Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250060786
    Abstract: A display device includes a substrate that includes a display area and a non-display area, a display layer disposed on the substrate and overlapping the display area, and a support plate disposed under the substrate. The support plate includes a first region disposed on a rear surface of the display layer, a second region connected to the first region and including a lattice pattern, and a third region connected to the second region and disposed on a rear surface of the first region. The second region is bent and overlaps a bending area of the non-display area of the substrate.
    Type: Application
    Filed: March 7, 2024
    Publication date: February 20, 2025
    Applicant: Samsung Display Co., LTD.
    Inventors: Su Chang RYU, Sung Guk AN, HYEONG-JUN KIM, Suk Ho CHOI, Jung Kyu CHOI
  • Publication number: 20250046674
    Abstract: A module comprising: a module substrate; a system-on-chip die coupled to the module substrate; a thermal interface material layer coupled to the system-on-chip die; a stiffener structure positioned around the system-on-chip die and coupled to the module substrate; and a lid having a first portion coupled to the thermal interface material layer, a second portion coupled to the stiffener structure and a recessed region formed around the first portion and having a reduced thickness relative to the first portion and the second portion.
    Type: Application
    Filed: August 3, 2023
    Publication date: February 6, 2025
    Inventors: Suk-Kyu Ryu, Wei Hu, Jie-Hua Zhao, Myung Jin Yim
  • Publication number: 20240421126
    Abstract: Integrated circuit (IC) structures, electronic modules, and methods of fabrication are described in which direct bonded interfaces are removed at corners or edges to counteract the potential for non-bonding or delamination. This can be accomplished during singulation, in which a side recess is formed through an entire thickness of an electronic component and into a direct bonded die, followed by final singulation of the IC structure.
    Type: Application
    Filed: March 7, 2024
    Publication date: December 19, 2024
    Inventors: Chi Nung Ni, Wei Chen, Weiming Chris Chen, Vidhya Ramachandran, Jie-Hua Zhao, Suk-Kyu Ryu, Myung Jin Yim, Chih-Ming Chung, Jun Zhai, Young Doo Jeon, Seungjae Lee
  • Publication number: 20240249989
    Abstract: Microelectronic structures with selectively applied underfill material and/or edge bond material are described. In an embodiment, isolated underfill regions and/or edge bond regions are applied to adjacent to one or more edges of an electronic device and form a plurality of vent openings along the one or more edges.
    Type: Application
    Filed: January 23, 2023
    Publication date: July 25, 2024
    Inventors: Wei Chen, Balaji Nandhivaram Muthuraman, Arun Sasi, Jie-Hua Zhao, Suk-Kyu Ryu, Jun Zhai, Dominic Morache, Young Doo Jeon
  • Publication number: 20240039539
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Application
    Filed: October 5, 2023
    Publication date: February 1, 2024
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • Patent number: 11831312
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: November 28, 2023
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • Publication number: 20220231687
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Application
    Filed: February 23, 2022
    Publication date: July 21, 2022
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • Patent number: 11309895
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: April 19, 2022
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • Publication number: 20200389172
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 10, 2020
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • Patent number: 10742217
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: August 11, 2020
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • Publication number: 20190319626
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Application
    Filed: February 4, 2019
    Publication date: October 17, 2019
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu