Abstract: The connector of the Present Disclosure for a flexible circuit cable comprises a housing on the front whereof is formed an insertion slot for a flexible circuit cable, and on the front and rear whereof is formed a terminal insertion hole; a plurality of contact terminals inserted into the front and rear of the housing via the terminal insertion holes; an actuator that pivots around a pivot axis and, when in closed position, creates electrical contact between the contact terminal and the conductor part of the flexible circuit cable by pressing the inserted flexible circuit cable down and into the housing; and a molded dust cover that pivots with the actuator and is installed on the housing to enable rotation and thus prevent the introduction of dust; and has a structure wherein on either end part of the molded dust cover is formed a rotation axis groove, and rotation axis projections are formed on either side of the housing to enable coupling with the rotation axis grooves.

Abstract: A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous to the first mat, a first sense amplifier coupled to a first bit line of the first mat, a second sense amplifier coupled to a second bit line of the first mat and a third bit line of the second mat, a third sense amplifier coupled to a fourth bit line of the second mat, and a plurality of bit line precharge voltage providers for varying a level of a bit line precharge voltage provided to the first, second, and third sense amplifiers, selectively providing the resultant bit line precharge voltage level, and providing the same voltage as that of data of a selected cell to a non-selected sense amplifier during a read operation.

Abstract: A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous to the first mat, a first sense amplifier coupled to a first bit line of the first mat, a second sense amplifier coupled to a second bit line of the first mat and a third bit line of the second mat, a third sense amplifier coupled to a fourth bit line of the second mat, and a plurality of bit line precharge voltage providers for varying a level of a bit line precharge voltage provided to the first, second, and third sense amplifiers, selectively providing the resultant bit line precharge voltage level, and providing the same voltage as that of data of a selected cell to a non-selected sense amplifier during a read operation.

Abstract: A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous to the first mat, a first sense amplifier coupled to a first bit line of the first mat, a second sense amplifier coupled to a second bit line of the first mat and a third bit line of the second mat, a third sense amplifier coupled to a fourth bit line of the second mat, and a plurality of bit line precharge voltage providers for varying a level of a bit line precharge voltage provided to the first, second, and third sense amplifiers, selectively providing the resultant bit line precharge voltage level, and providing the same voltage as that of data of a selected cell to a non-selected sense amplifier during a read operation.

Abstract: A technology is a semiconductor device and a method of manufacturing the same, capable of reducing capacitance with a storage node contact plug while maintaining a height and resistance of a bit line, by thickly forming a spacer between a bit line and the storage node contact plug. A semiconductor device includes a device isolation layer defining a plurality of active regions formed in a semiconductor substrate, a storage node contact hole exposing two neighboring active regions, a storage node contact plug material provided in the storage node contact hole, a bit line region that divides the storage node contact plug material into two parts and that has a convex portion at a lower portion of a sidewall, a spacer formed over a sidewall of the bit line region including the convex portion and a bit line formed in the bit line region.

Abstract: A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous to the first mat, a first sense amplifier coupled to a first bit line of the first mat, a second sense amplifier coupled to a second bit line of the first mat and a third bit line of the second mat, a third sense amplifier coupled to a fourth bit line of the second mat, and a plurality of bit line precharge voltage providers for varying a level of a bit line precharge voltage provided to the first, second, and third sense amplifiers, selectively providing the resultant bit line precharge voltage level, and providing the same voltage as that of data of a selected cell to a non-selected sense amplifier during a read operation.

Abstract: A technology is a semiconductor device and a method of manufacturing the same, capable of reducing capacitance with a storage node contact plug while maintaining a height and resistance of a bit line, by thickly forming a spacer between a bit line and the storage node contact plug. A semiconductor device includes a device isolation layer defining a plurality of active regions formed in a semiconductor substrate, a storage node contact hole exposing two neighboring active regions, a storage node contact plug material provided in the storage node contact hole, a bit line region that divides the storage node contact plug material into two parts and that has a convex portion at a lower portion of a sidewall, a spacer formed over a sidewall of the bit line region including the convex portion and a bit line formed in the bit line region.

Abstract: Provided is a bulb socket. The bulb socket includes a housing formed as a single piece using a single mold assembly, a couple of lamp holders, a double contact terminal, and a single contact terminal.

Abstract: The present invention provides a method of fabricating a semiconductor apparatus including a vertical transistor and a semiconductor apparatus fabricated thereby which protect a pillar-shaped channel region to stabilize an operating characteristic of the semiconductor apparatus. The method of fabricating the semiconductor apparatus according to the present invention comprises: forming a pillar-shaped pattern on a semiconductor substrate; depositing a conductive layer surrounding the pattern; changing a feature of some portion of the conductive layer through an ion implanting process to form an oxide film; and removing the oxide film using an etching selectivity difference.

Abstract: Provided is a bulb socket. The bulb socket includes a housing formed as a single piece using a single mold assembly, a couple of lamp holders, a double contact terminal, and a single contact terminal.

Abstract: The present invention provides a method of fabricating a semiconductor apparatus including a vertical transistor and a semiconductor apparatus fabricated thereby which protect a pillar-shaped channel region to stabilize an operating characteristic of the semiconductor apparatus. The method of fabricating the semiconductor apparatus according to the present invention comprises: forming a pillar-shaped pattern on a semiconductor substrate; depositing a conductive layer surrounding the pattern; changing a feature of some portion of the conductive layer through an ion implanting process to form an oxide film; and removing the oxide film using an etching selectivity difference.

Abstract: An automatic journalizing method and system enable even a novice in accounting to conduct automatic journalizing of transaction data by employing a reverse-journalizing technique. Further, the automatic journalizing method and system are capable of conducting exact journalizing by using preset binary transaction classification criteria. Further, by integrating multi-aspects of transaction classification including fundamental characteristics of transaction, original characteristics of journalizing and simplicity/complicacy characteristics of transaction, the automatic journalizing method and system allow even the novice to correctly perform automatic journalizing for both a simple and a complex transaction.