Abstract: A method for fabricating a capacitor useful for ultra large scale integration semiconductor devices of 64M DRAM or larger, comprising the steps of: laminating a plurality of insulating layers which are different in etch selection ratio from one another; selectively etching the insulating layers to make a cavity between the insulating layers; depositing a polysilicon layer for a storage electrode over the resulting structure, to fill the cavity; and subjecting the polysilicon layer to etch back to form a spacer.

Abstract: A method for fabricating capacitors of a semiconductor device capable of increasing the surface area of the storage electrode using both an adjustment for the dimension of a contact mask for the storage electrode and a technique of selective growth, thereby achieving an improvement in capacitance. The method includes the steps of forming a storage electrode with an increased surface area using the technique for adjusting the contact mask dimension, the technique of selective growth and a wet etch process, and then forming a dielectric film and a plate electrode over the storage electrode.