Patents by Inventor Sukalpa Biswas

Sukalpa Biswas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210125657
    Abstract: In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.
    Type: Application
    Filed: January 4, 2021
    Publication date: April 29, 2021
    Inventors: Sukalpa Biswas, Farid Nemati
  • Patent number: 10929222
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: February 23, 2021
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Patent number: 10916290
    Abstract: In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: February 9, 2021
    Assignee: Apple Inc.
    Inventors: Sukalpa Biswas, Farid Nemati
  • Patent number: 10901617
    Abstract: A memory controller circuit coupled to a memory circuit that includes multiple banks may receive multiple access requests including a particular access request to a particular bank of the plurality of banks. The particular access request is associated with a particular virtual channel of a plurality of virtual channels. The memory controller circuit may select a given access requests of the multiple access requests based on an arbitration category value associated with a virtual channel of the given access request and modify the arbitration category value in response to selecting the given access request.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: January 26, 2021
    Assignee: Apple Inc.
    Inventors: Gregory S. Mathews, Shane J. Keil, Sukalpa Biswas, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijavaraj
  • Patent number: 10872652
    Abstract: A method and apparatus for optimizing calibrations of a memory subsystem is disclosed. A memory controller of a memory subsystem includes a memory interface suitable for coupling to a DRAM having a plurality of banks. The memory controller includes a state machine the state machine may initiate calibration of circuitry within the memory controller. Responsive to initiating the calibration, the state machine also causes a refresh command to be transmitted to the DRAM. The calibration is then performed concurrent with the refresh of the DRAM. Subsequent to transmitting the refresh command, the state machine causes the memory interface to be placed into a low power state.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 22, 2020
    Assignee: Apple Inc.
    Inventors: Rakesh L. Notani, Lakshmi Narasimha Murthy Nukala, Kai Lun Hsiung, Sukalpa Biswas, Yanzhe Liu
  • Patent number: 10838884
    Abstract: A memory controller circuit coupled to multiple memory circuits may receive requests to access particular locations within the multiple memory circuits. A request may be assigned a particular quality-of-service level. During operation, the memory controller circuit may reallocate the quality-of-service level of a particular request to a new quality-of-service level based on accumulated bandwidth credits associated with the new quality-of-service level.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: November 17, 2020
    Assignee: Apple Inc.
    Inventors: Thejasvi Magudilu Vijavaraj, Sukalpa Biswas, Lakshmi narasimha murthy Nukala, Gregory S. Mathews
  • Patent number: 10817219
    Abstract: A memory controller circuit coupled to multiple memory circuits may receive a read request for a particular one of the memory circuits and insert the read request into one of multiple linked lists that includes a linked list whose entries correspond to previously received read requests and are linked according to respective ages of the read requests. The memory controller circuit may schedule the read request using a head pointer of one of the multiple linked lists.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 27, 2020
    Assignee: Apple Inc.
    Inventors: Lakshmi Narasimha Murthy Nukala, Sukalpa Biswas, Thejasvi Magudilu Vijavaraj, Shane J. Keil, Gregory S. Mathews
  • Patent number: 10802968
    Abstract: An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: October 13, 2020
    Assignee: Apple Inc.
    Inventors: Sukalpa Biswas, Harshavardhan Kaushikkar, Munetoshi Fukami, Gurjeet S. Saund, Manu Gulati, Shinye Shiu
  • Publication number: 20200301615
    Abstract: An apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Shane J. Keil, Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung, Yanzhe Liu, Sukalpa Biswas
  • Patent number: 10678478
    Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: June 9, 2020
    Assignee: Apple Inc.
    Inventors: Shane J. Keil, Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung, Yanzhe Liu, Sukalpa Biswas
  • Publication number: 20200159463
    Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.
    Type: Application
    Filed: January 24, 2020
    Publication date: May 21, 2020
    Inventors: Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Peter Fu, Rakesh L. Notani, Sukalpa Biswas, Thejasvi Magudilu Vijayaraj, Yanzhe Liu, Shane J. Keil
  • Publication number: 20200143866
    Abstract: In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: Sukalpa Biswas, Farid Nemati
  • Patent number: 10642740
    Abstract: In an embodiment, an apparatus includes multiple memory resources, and a resource table that includes entries that correspond to respective memory resources of the multiple memory resources. The apparatus also includes a circuit configured to receive a first memory command. The first memory command is associated with a subset of the multiple memory resources. For each memory resource of the subset, the circuit is also configured to set a respective indicator associated with the first memory command, and to store a first value in a first entry of the resource table in response to a determination that the respective memory resource is unavailable. The circuit is also configured to store a second value in each entry of the resource table that corresponds to a memory resource of the subset in response to a determination that an entry corresponding to a given memory resource of the subset includes the first value.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: May 5, 2020
    Assignee: Apple Inc.
    Inventors: Bikram Saha, Harshavardhan Kaushikkar, Sukalpa Biswas, Prashant Jain
  • Publication number: 20200081652
    Abstract: A memory controller circuit coupled to multiple memory circuits may receive a read request for a particular one of the memory circuits and insert the read request into one of multiple linked lists that includes a linked list whose entries correspond to previously received read requests and are linked according to respective ages of the read requests. The memory controller circuit may schedule the read request using a head pointer of one of the multiple linked lists.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 12, 2020
    Inventors: Lakshmi Narasimha Murthy Nukala, Sukalpa Biswas, Thejasvi Magudilu Vijavaraj, Shane J. Keil, Gregory S. Mathews
  • Publication number: 20200081622
    Abstract: A memory controller circuit coupled to a memory circuit that includes multiple banks may receive multiple access requests including a particular access request to a particular bank of the plurality of banks. The particular access request is associated with a particular virtual channel of a plurality of virtual channels. The memory controller circuit may select a given access requests of the multiple access requests based on an arbitration category value associated with a virtual channel of the given access request and modify the arbitration category value in response to selecting the given access request.
    Type: Application
    Filed: September 9, 2019
    Publication date: March 12, 2020
    Inventors: Gregory S. Mathews, Shane J. Keil, Sukalpa Biswas, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijavaraj
  • Publication number: 20200065028
    Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Inventors: Shane J. Keil, Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung, Yanzhe Liu, Sukalpa Biswas
  • Patent number: 10573368
    Abstract: In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: February 25, 2020
    Assignee: Apple Inc.
    Inventors: Sukalpa Biswas, Farid Nemati
  • Publication number: 20200057579
    Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller implements a per-bank priority-based arbitration scheme for different types of memory traffic (e.g., with different quality of service parameters). In some embodiments, the memory controller is configured to provide per-bank overrides to the arbitration scheme based on latency tolerance reported by one or more requesters sending a particular type of memory traffic. Various techniques disclosed herein may improve performance, improve fairness among different types of memory traffic, and/or reduce power consumption.
    Type: Application
    Filed: August 17, 2018
    Publication date: February 20, 2020
    Inventors: Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Peter Fu, Rakesh L. Notani, Sukalpa Biswas, Thejasvi Magudilu Vijayaraj, Yanzhe Liu, Shane J. Keil
  • Patent number: 10545701
    Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller implements a per-bank priority-based arbitration scheme for different types of memory traffic (e.g., with different quality of service parameters). In some embodiments, the memory controller is configured to provide per-bank overrides to the arbitration scheme based on latency tolerance reported by one or more requesters sending a particular type of memory traffic. Various techniques disclosed herein may improve performance, improve fairness among different types of memory traffic, and/or reduce power consumption.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: January 28, 2020
    Assignee: Apple Inc.
    Inventors: Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Peter Fu, Rakesh L. Notani, Sukalpa Biswas, Thejasvi Magudilu Vijayaraj, Yanzhe Liu, Shane J. Keil
  • Publication number: 20200004444
    Abstract: An embodiment of an apparatus includes a plurality of processing circuits, a plurality of memory circuits, and a memory controller circuit coupled to each memory circuit via a respective communication channel. A particular processing circuit may generate a data stream that includes a plurality of data blocks. The memory controller circuit may receive the plurality of data blocks from the particular processing circuit. The memory controller circuit may distribute the plurality of data blocks among the plurality of memory circuits based on respective utilizations of the plurality of communication channels.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Sukalpa Biswas, Thejasvi Magudilu Vijayarai