Patents by Inventor Sukalpa Biswas

Sukalpa Biswas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190286519
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Application
    Filed: May 7, 2019
    Publication date: September 19, 2019
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Patent number: 10318377
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: June 11, 2019
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Patent number: 10310586
    Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 4, 2019
    Assignee: Apple Inc.
    Inventors: Sukalpa Biswas, Shinye Shiu, Cyril de la Cropte de Chanterac, Manu Gulati, Pulkit Desai, Rong Zhang Hu
  • Publication number: 20190042492
    Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.
    Type: Application
    Filed: July 9, 2018
    Publication date: February 7, 2019
    Inventors: Robert E. Jeter, Brijesh Tripathi, Kiran Kattel, Rakesh L. Notani, Fabien S. Faure, Sukalpa Biswas, Kai Lun Hsiung, Neeraj Parik, Venkata Ramana Malladi, Shiva Kumar, Chaitanya Polapragada, Allen Kim
  • Patent number: 10175905
    Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: January 8, 2019
    Assignee: Apple Inc.
    Inventors: Robert E. Jeter, Liang Deng, Kai Lun Hsiung, Manu Gulati, Rakesh L. Notani, Sukalpa Biswas, Venkata Ramana Malladi, Gregory S. Mathews, Enming Zheng, Fabien S. Faure
  • Publication number: 20180314592
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Application
    Filed: July 9, 2018
    Publication date: November 1, 2018
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Publication number: 20180276128
    Abstract: In an embodiment, an apparatus includes multiple memory resources, and a resource table that includes entries that correspond to respective memory resources of the multiple memory resources. The apparatus also includes a circuit configured to receive a first memory command. The first memory command is associated with a subset of the multiple memory resources. For each memory resource of the subset, the circuit is also configured to set a respective indicator associated with the first memory command, and to store a first value in a first entry of the resource table in response to a determination that the respective memory resource is unavailable. The circuit is also configured to store a second value in each entry of the resource table that corresponds to a memory resource of the subset in response to a determination that an entry corresponding to a given memory resource of the subset includes the first value.
    Type: Application
    Filed: June 4, 2018
    Publication date: September 27, 2018
    Inventors: Bikram Saha, Harshavardhan Kaushikkar, Sukalpa Biswas, Prashant Jain
  • Patent number: 10042701
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: August 7, 2018
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Patent number: 10019387
    Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: July 10, 2018
    Assignee: Apple Inc.
    Inventors: Robert E. Jeter, Brijesh Tripathi, Kiran Kattel, Rakesh L. Notani, Fabien S. Faure, Sukalpa Biswas, Kai Lun Hsiung, Neeraj Parik, Venkata Ramana Malladi, Shiva Kumar, Chaitanya Polapragada, Allen Kim
  • Patent number: 10013046
    Abstract: Systems, apparatuses, and methods for improved power management techniques. An apparatus may include a display control unit, a communication fabric, a memory controller, a memory cache, and a memory. When the memory is power-gated, and the display control unit needs to fetch pixel data, the display control unit may send a wake-up signal to the memory before sending a wake-up signal to the communication fabric. The display control unit may then issue the pixel fetch request later. Additionally, if the display control unit determines that the pixel data has a high probability of being cached, then the display control unit may not send a wake-up signal to the memory, and the display control unit may issue the request earlier. More generally, the display control unit may send wake-up signals to multiple components in a manner which accounts for the wake-up latency of each component.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 3, 2018
    Assignee: Apple Inc.
    Inventors: Peter F. Holland, Hao Chen, Sukalpa Biswas
  • Patent number: 9990294
    Abstract: In an embodiment, an apparatus includes multiple memory resources, and a resource table that includes entries that correspond to respective memory resources of the multiple memory resources. The apparatus also includes a circuit configured to receive a first memory command. The first memory command is associated with a subset of the multiple memory resources. For each memory resource of the subset, the circuit is also configured to set a respective indicator associated with the first memory command, and to store a first value in a first entry of the resource table in response to a determination that the respective memory resource is unavailable. The circuit is also configured to store a second value in each entry of the resource table that corresponds to a memory resource of the subset in response to a determination that an entry corresponding to a given memory resource of the subset includes the first value.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: June 5, 2018
    Assignee: Apple Inc.
    Inventors: Bikram Saha, Harshavardhan Kaushikkar, Sukalpa Biswas, Prashant Jain
  • Publication number: 20180074743
    Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.
    Type: Application
    Filed: September 13, 2016
    Publication date: March 15, 2018
    Inventors: Robert E. Jeter, Liang Deng, Kai Lun Hsiung, Manu Gulati, Rakesh L. Notani, Sukalpa Biswas, Venkata Ramana Malladi, Gregory S. Mathews, Enming Zheng, Fabien S. Faure
  • Publication number: 20180061484
    Abstract: In an embodiment, an integrated circuit (IC) and a memory device are configured to operate in a “normal” mode and a “self refresh” mode. The IC may generate refresh commands according to a refresh interval during normal mode. The memory device may be responsible for refresh during the self refresh mode. The IC may ensure that the amount of time that has expired in the current refresh interval prior to entering self refresh mode is retained, so that a remaining amount of time may expire after self refresh mode is exited prior to generating the initial refresh command after exiting self refresh mode. Similarly, the memory device may retain the amount of time that has expired in the current self refresh interval prior to exiting self refresh, so that a remaining amount of time may expire after self refresh mode is entered again prior to performing an initial self refresh.
    Type: Application
    Filed: March 7, 2017
    Publication date: March 1, 2018
    Inventor: Sukalpa Biswas
  • Publication number: 20170322614
    Abstract: Systems, apparatuses, and methods for improved power management techniques. An apparatus may include a display control unit, a communication fabric, a memory controller, a memory cache, and a memory. When the memory is power-gated, and the display control unit needs to fetch pixel data, the display control unit may send a wake-up signal to the memory before sending a wake-up signal to the communication fabric. The display control unit may then issue the pixel fetch request later. Additionally, if the display control unit determines that the pixel data has a high probability of being cached, then the display control unit may not send a wake-up signal to the memory, and the display control unit may issue the request earlier. More generally, the display control unit may send wake-up signals to multiple components in a manner which accounts for the wake-up latency of each component.
    Type: Application
    Filed: May 9, 2016
    Publication date: November 9, 2017
    Inventors: Peter F. Holland, Hao Chen, Sukalpa Biswas
  • Publication number: 20170242798
    Abstract: In an embodiment, an apparatus includes multiple memory resources, and a resource table that includes entries that correspond to respective memory resources of the multiple memory resources. The apparatus also includes a circuit configured to receive a first memory command. The first memory command is associated with a subset of the multiple memory resources. For each memory resource of the subset, the circuit is also configured to set a respective indicator associated with the first memory command, and to store a first value in a first entry of the resource table in response to a determination that the respective memory resource is unavailable. The circuit is also configured to store a second value in each entry of the resource table that corresponds to a memory resource of the subset in response to a determination that an entry corresponding to a given memory resource of the subset includes the first value.
    Type: Application
    Filed: February 24, 2016
    Publication date: August 24, 2017
    Inventors: Bikram Saha, Harshavardhan Kaushikkar, Sukalpa Biswas, Prashant Jain
  • Publication number: 20170091026
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Application
    Filed: September 22, 2016
    Publication date: March 30, 2017
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Publication number: 20160328322
    Abstract: An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.
    Type: Application
    Filed: May 6, 2015
    Publication date: November 10, 2016
    Inventors: Sukalpa Biswas, Harshavardhan Kaushikkar, Munetoshi Fukami, Gurjeet S. Saund, Manu Gulati, Shinye Shiu
  • Patent number: 9478263
    Abstract: Systems and methods for monitoring and controlling repetitive accesses to a dynamic random-access memory (DRAM) row are disclosed. A method for monitoring and controlling repetitive accesses to a DRAM can include dividing a bank of the DRAM into a number of logical blocks, mapping each row of the bank to one of the logical blocks, monitoring accesses to the logical blocks, and controlling accesses to the logical blocks based on the monitoring.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 25, 2016
    Assignee: APPLE INC.
    Inventors: Bin Ni, Kai Lun Charles Hsiung, Yanzhe Liu, Sukalpa Biswas
  • Patent number: 9477259
    Abstract: A method and apparatus for calibration of a clock signal used in data transmission is disclosed. The method includes a calibration having coarse and fine grain procedures. The coarse grain procedure begins from the center of a current eye and performs reads while decrementing the delay provided to the clock signal until at least one bit fails. This is repeated, from the center of the eye, incrementing until again at least one bit fails. The lower and upper last passing points are recorded. A fine grain procedure includes performing reads while decrementing, from the lower last passing point, recording points at which each bit fails until all fail. The fine grain procedure further includes incrementing, from the upper last passing point, recording points at which each bit fails until fail. Thereafter, a clock delay corresponding to the center of the new eye is determined based on the calibration data.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: October 25, 2016
    Assignee: Apple Inc.
    Inventors: Robert E. Jeter, Neeraj Parik, Sukalpa Biswas
  • Publication number: 20160292094
    Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 6, 2016
    Inventors: Robert E. Jeter, Brijesh Tripathi, Kiran Kattel, Rakesh L. Notani, Fabien S. Faure, Sukalpa Biswas, Kai Lun Hsiung, Neeraj Parik, Venkata Ramana Malladi, Shiva Kumar, Chaitanya Polapragada, Allen Kim