Patents by Inventor Sukanta Kishore Panigrahi
Sukanta Kishore Panigrahi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9705393Abstract: A method of operating a voltage regulator including a source voltage rail and a plurality of output voltage rails, the method including: converting a source voltage on the source voltage rail to a respective output voltage on each output voltage rail; selecting an output voltage rail; comparing the output voltage on the selected output voltage rail to a reference voltage for the selected output voltage rail; and if the output voltage of the selected output voltage rail is less than the reference voltage for the selected output voltage rail, controlling the voltage regulator to increase the output voltage on the selected output voltage rail, wherein the frequency at which an output voltage rail is selected is dependent upon the rate at which the voltage regulator has previously increased the output voltage on that output voltage rail.Type: GrantFiled: December 30, 2013Date of Patent: July 11, 2017Assignee: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.Inventors: Barnaby Golder, Peter Andrew Rees Williams, Sukanta Kishore Panigrahi, Timothy Charles Clapp, Richard Andrew Wilkinson
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Patent number: 9369033Abstract: A switched mode power supply for supplying power from a power source to one or more output voltage rails, including: a switching unit configured to receive a source voltage from the power source and to output a switched voltage, the switching unit including: a first switch configured to switch the source voltage to the switched voltage, and configured to be driven by the source voltage; and a second switch connected in parallel with the first switch, the second switch configured to switch the source voltage to the switched voltage, and configured to be driven by an output voltage of one of the output voltage rails.Type: GrantFiled: December 31, 2013Date of Patent: June 14, 2016Assignee: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.Inventor: Sukanta Kishore Panigrahi
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Publication number: 20150188407Abstract: A method of operating a voltage regulator including a source voltage rail and a plurality of output voltage rails, the method including: converting a source voltage on the source voltage rail to a respective output voltage on each output voltage rail; selecting an output voltage rail; comparing the output voltage on the selected output voltage rail to a reference voltage for the selected output voltage rail; and if the output voltage of the selected output voltage rail is less than the reference voltage for the selected output voltage rail, controlling the voltage regulator to increase the output voltage on the selected output voltage rail, wherein the frequency at which an output voltage rail is selected is dependent upon the rate at which the voltage regulator has previously increased the output voltage on that output voltage rail.Type: ApplicationFiled: December 30, 2013Publication date: July 2, 2015Applicant: Cambridge Silicon Radio LimitedInventors: Barnaby Golder, Peter Andrew Rees Williams, Sukanta Kishore Panigrahi, Timothy Charles Clapp, Richard Andrew Wilkinson
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Publication number: 20150188402Abstract: A switched mode power supply for supplying power from a power source to one or more output voltage rails, including: a switching unit configured to receive a source voltage from the power source and to output a switched voltage, the switching unit including: a first switch configured to switch the source voltage to the switched voltage, and configured to be driven by the source voltage; and a second switch connected in parallel with the first switch, the second switch configured to switch the source voltage to the switched voltage, and configured to be driven by an output voltage of one of the output voltage rails.Type: ApplicationFiled: December 31, 2013Publication date: July 2, 2015Applicant: Cambridge Silicon Radio LimitedInventor: Sukanta Kishore Panigrahi
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Patent number: 8035407Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.Type: GrantFiled: April 4, 2011Date of Patent: October 11, 2011Assignee: Texas Instruments IncorporatedInventors: James Michael Jarboe, Jr., Sukanta Kishore Panigrahi, Vinay Agrawal, Neeraj P. Nayak
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Publication number: 20110176374Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.Type: ApplicationFiled: April 4, 2011Publication date: July 21, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: James Michael Jarboe, JR., Sukanta Kishore Panigrahi, Vinay Agrawal, Neeraj P. Nayak
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Patent number: 7940066Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.Type: GrantFiled: October 13, 2010Date of Patent: May 10, 2011Assignee: Texas Instruments IncorporatedInventors: James Michael Jarboe, Jr., Sukanta Kishore Panigrahi, Vinay Agrawal, Neeraj P. Nayak
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Publication number: 20110026343Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.Type: ApplicationFiled: October 13, 2010Publication date: February 3, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: James Michael Jarboe, JR., Sukanta Kishore Panigrahi, Vinay Agrawal, Neeraj P. Nayak
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Patent number: 7834615Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.Type: GrantFiled: July 2, 2007Date of Patent: November 16, 2010Assignee: Texas Instruments IncorporatedInventors: James Michael Jarboe, Jr., Sukanta Kishore Panigrahi, Vinay Agrawal, Neeraj P. Nayak
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Publication number: 20090013228Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit comprises a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a plurality of sequential input/output bit-pair signals corresponding to an internal data strobe input signal and a phase shifted data strobe output signal respectively.Type: ApplicationFiled: July 2, 2007Publication date: January 8, 2009Inventors: JAMES MICHAEL JARBOE, JR., Sukanta Kishore Panigrahi, Vinay Agrawal, Neeraj P. Nayak
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Publication number: 20090009206Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit comprises a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a plurality of sequential input/output bit-pair signals corresponding to an internal data strobe input signal and a phase shifted data strobe output signal respectively.Type: ApplicationFiled: July 2, 2007Publication date: January 8, 2009Inventors: James Michael Jarboe, JR., Sukanta Kishore Panigrahi, Vinay Agrawal, Neeraj P. Nayak