Patents by Inventor Sukanto Ghosh

Sukanto Ghosh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9424165
    Abstract: Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, a forced halt sequence can be initiated, which causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 23, 2016
    Assignee: APPLIED MICRO CIRCUITS CORPORATION
    Inventors: Waseem Kraipak, Sukanto Ghosh
  • Patent number: 9268627
    Abstract: Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, halt detection logic can initiate a forced halt sequence that causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 23, 2016
    Assignee: Applied Micro Circuits Corporation
    Inventors: Waseem Kraipak, Sukanto Ghosh
  • Publication number: 20140281695
    Abstract: Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, halt detection logic can initiate a forced halt sequence that causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: APPLIED MICRO CIRCUITS CORPORATION
    Inventors: Waseem Kraipak, Sukanto Ghosh
  • Publication number: 20140281722
    Abstract: Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, a forced halt sequence can be initiated, which causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: APPLIED MICRO CIRCUITS CORPORATION
    Inventors: Waseem Kraipak, Sukanto Ghosh