Abstract: In a polishing head for a CMP apparatus, a stress distributing plate made of metal or ceramic is placed between a wafer on a polishing pad and an air bag configured to press down the wafer, and a shock absorbing sheet is provided between the stress distributing plate and the underlying wafer, to thereby make pressure applied from the air bag to the wafer uniform.

Abstract: A polishing head of a CMP apparatus includes a polishing pad, an air bag brought into contact with a rear surface of a wafer on the polishing pad and configured to press a front surface of the wafer against the polishing pad, and a top ring surrounding the air bag and the wafer. A portion of the air bag brought into contact with a peripheral portion of the wafer is thicker in film thickness than a portion of the air bag brought into contact with a central portion of the wafer. The polishing head is capable of applying even pressure to press down the wafer evenly throughout the entire wafer plane to improve the evenness of polishing.

Abstract: In a polishing head for a CMP apparatus, a stress distributing plate made of metal or ceramic is placed between a wafer on a polishing pad and an air bag configured to press down the wafer, and a shock absorbing sheet is provided between the stress distributing plate and the underlying wafer, to thereby make pressure applied from the air bag to the wafer uniform.

Abstract: Provided is a polishing head of a CMP apparatus that is improved in the evenness of polishing. The polishing head includes a polishing pad, an air bag brought into contact with a rear surface of a wafer on the polishing pad and is configured to press a front surface of the wafer against the polishing pad, and a top ring surrounding the air bag and the wafer. A portion of the air bag brought into contact with a peripheral portion of the wafer is thicker in film thickness than a portion of the air bag brought into contact with a central portion of the wafer.

Abstract: In order to prevent a crack from developing in an interlayer insulating film formed under a bonding pad due to impact forces, the bonding pad is formed so that small diameter metal plugs and large diameter metal plugs are arranged between a first metal film and a second metal film as an uppermost layer. Holes are formed in the centers of the larger diameter metal plugs and recessed portions are formed in surface areas of the second metal film above the large diameter metal plugs.

Abstract: In order to prevent a crack from developing in an interlayer insulating film formed under a bonding pad due to impact, the bonding pad is formed so that small diameter metal plugs (14a) and large diameter metal plugs (14b) are arranged between a first metal film (12) and a second metal film (15) as an uppermost layer, and recessed portions (17) are formed in a surface of the second metal film (15) above the large diameter metal plugs 14b.

Abstract: Provided is a semiconductor device having an ESD protection MOS transistor including a plurality of transistors combined together, in which a plurality of drain regions and a plurality of source regions disposed alternately and a gate electrode disposed between each pair of adjacent regions constituted of one of the plurality of drain regions and one of the plurality of source regions, in which a distance between a salicide metal region, which is formed on each of the plurality of drain regions, and the gate electrode is determined according to contact holes in the plurality of drain regions and a distance of the contact holes from substrate contacts.

Abstract: Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions and source regions placed alternately with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: the first metal interconnects formed on the source regions are electrically connected to the second metal interconnect through constant size via-holes, and a ratio between the numbers of the via-holes arranged above each of the source regions is controlled to be less than four according to a distance from the ground potential supply line.

Abstract: To prevent generation of cracks in an insulating film provided under a bonding pad, a semiconductor device includes a three-layered bonding pad, and the three-layered bonding pad includes a first metal film, a second metal film, and a third metal film, in which the second metal film has a Young's modulus higher than a Young's modulus of the first metal film and a Young's modulus of the third metal film.

Abstract: Provided is a semiconductor device having an ESD protection MOS transistor including a plurality of transistors combined together, in which a plurality of drain regions and a plurality of source regions disposed alternately and a gate electrode disposed between each pair of adjacent regions constituted of one of the plurality of drain regions and one of the plurality of source regions, in which a distance between a salicide metal region, which is formed on each of the plurality of drain regions, and the gate electrode is determined according to contact holes in the plurality of drain regions and a distance of the contact holes from substrate contacts.

Abstract: A semiconductor device has a silicon substrate, an external connection terminal disposed on the silicon substrate, an internal circuit region disposed on the silicon substrate, an NMOS transistor for electrostatic discharge protection provided between the external connection terminal and the internal circuit region, and a wiring connecting together the external connection terminal and the NMOS transistor and connecting together the NMOS transistor and the internal circuit region. The NMOS transistor has a drain region and a gate electrode whose potential is fixed to a ground potential. The external connection terminal is smaller than the drain region and is formed above the drain region.

Abstract: Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips.

Abstract: Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions and source regions placed alternately with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: the first metal interconnects formed on the source regions are electrically connected to the second metal interconnect through constant size via-holes, and a ratio between the numbers of the via-holes arranged above each of the source regions is controlled to be less than four according to a distance from the ground potential supply line.

Abstract: Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions connected with a first metal interconnect and source regions connected with another first metal interconnect alternately placed with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: at least one of the first metal interconnect and the other first metal interconnect being connected to a plurality of layers of metal interconnects other than the first metal interconnect; and the source regions include via-holes for electrically connecting the other first metal interconnect and the plurality of layers of metal interconnects other than the first metal interconnect, a greater number of the via-holes is formed as a distance of an interconnect connected to the NMOS transistor for ESD protection becomes larger.

Abstract: Provided is a semiconductor device having a trench isolation structure and a high power supply voltage circuit section including at least a well region and a MOS transistor formed therein. The high power supply voltage circuit section includes a carrier capture region for preventing latch-up in a vicinity of an end portion of the well region, and a depth of the carrier capture region is larger than a depth of the trench isolation region. The carrier capture region in the high power supply voltage circuit section is formed of a diffusion layer which is the same as that of a source or a drain region of the MOS transistor formed in the high power supply voltage circuit section.

Abstract: In a semiconductor device including, between an external connection terminal and an internal circuit region, an NMOS transistor for ESD protection having a gate potential fixed to a ground potential, the external connection terminal is formed above a drain region of the NMOS transistor for ESD protection, and the drain region is surrounded by a source region through a channel region. Further, the drain region has a shape with rounded corners in plan view.

Abstract: Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips.

Abstract: Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips.

Abstract: Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions connected with a first metal interconnect and source regions connected with another first metal interconnect alternately placed with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: at least one of the first metal interconnect and the other first metal interconnect being connected to a plurality of layers of metal interconnects other than the first metal interconnect; and the source regions include via-holes for electrically connecting the other first metal interconnect and the plurality of layers of metal interconnects other than the first metal interconnect, a greater number of the via-holes is formed as a distance of an interconnect connected to the NMOS transistor for ESD protection becomes larger.

Abstract: Provided is a semiconductor device having a trench isolation structure and a high power supply voltage circuit section including at least a well region and a MOS transistor formed therein. The high power supply voltage circuit section includes a carrier capture region for preventing latch-up in a vicinity of an end portion of the well region, and a depth of the carrier capture region is larger than a depth of the trench isolation region. The carrier capture region in the high power supply voltage circuit section is formed of a diffusion layer which is the same as that of a source or a drain region of the MOS transistor formed in the high power supply voltage circuit section.