Patents by Inventor Sukesh Mohan

Sukesh Mohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus employing integrated metrology for improved dielectric etch efficiency
    Patent number: 7265382
    Abstract: A method and apparatus for processing a semiconductor wafer is provided for reducing dimensional variation by feeding forward information relating to photoresist mask CD and profile and underlying layer thickness measured at several points on the wafer to adjust the next process the inspected wafer will undergo (e.g., the etch process). After the processing step, dimensions of a structure formed by the process, such as the CD and depth of a trench formed by the process, are measured at several points on the wafer, and this information is fed back to the process tool to adjust the process for the next wafer to further reduce dimensional variation. In certain embodiments, the CD, profile, thickness and depth measurements, etch processing and post-etch cleaning are performed at a single module in a controlled environment.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: September 4, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Dimitris Lymberopoulos, Gary Hsueh, Sukesh Mohan
  • Method and apparatus employing integrated metrology for improved dielectric etch efficiency
    Publication number: 20040092047
    Abstract: A method and apparatus for processing a semiconductor wafer is provided for reducing dimensional variation by feeding forward information relating to photoresist mask CD and profile and underlying layer thickness measured at several points on the wafer to adjust the next process the inspected wafer will undergo (e.g., the etch process). After the processing step, dimensions of a structure formed by the process, such as the CD and depth of a trench formed by the process, are measured at several points on the wafer, and this information is fed back to the process tool to adjust the process for the next wafer to further reduce dimensional variation. In certain embodiments, the CD, profile, thickness and depth measurements, etch processing and post-etch cleaning are performed at a single module in a controlled environment.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 13, 2004
    Applicant: Applied Materials,Inc.
    Inventors: Dimitris Lymberopoulos, Gary Hsueh, Sukesh Mohan